| Biblio | A Highly Integrated Dual-Path Step-Down Hybrid DC–DC Converter With Self-Balanced Flying Capacitor and Reduced Inductor Current | %1 | 0 | 1 week 6 days ago |
| Biblio | A 5-7 GHz BiCMOS Front-End Module for WiFi 6e with 2.2 dB NF and 16 dBm PAVG at −40 dB EVM | %1 | 0 | 2 months 4 days ago |
| Biblio | Accurate Analysis of Switching Transients in the High-Frequency, Integrated Dual-Path Step-Down DC-DC Converter | %1 | 0 | 2 months 4 days ago |
| Biblio | A 0.13-μm HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication | %1 | 0 | 3 months 3 days ago |
| Biblio | A Study of the Efficiency of Output-Matched Radiofrequency Power Amplifiers | %1 | 0 | 3 months 3 days ago |
| Biblio | Analysis of a gm-C Complex Filter for Low Power Wireless Receivers | %1 | 0 | 3 months 3 days ago |
| Biblio | A DLL-Based FSK Demodulator for Asynchronous Communications | %1 | 0 | 3 months 3 days ago |
| Biblio | Analysis of a Three-Way Voltage-Mode Digital Doherty Power Amplifier for Bluetooth Applications | %1 | 0 | 3 months 3 days ago |
| Biblio | A Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication | %1 | 0 | 4 months 2 days ago |
| Biblio | A 0.7 V Multi-Class Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22 nm CMOS | %1 | 0 | 4 months 5 days ago |
| Biblio | On the Upconversion of the Cross-Coupled Pair 1/f Noise Into Phase Noise in Current-Biased Class-B CMOS Oscillators | %1 | 0 | 4 months 3 weeks ago |
| Biblio | A 5.75mW Fully-Integrated Galvanic Isolator for Gate Drivers with Asynchronous 66.7/66.7 Mb/s Full-Duplex Communication | %1 | 0 | 5 months 6 days ago |
| Biblio | A Driving Methodology for Four-Quadrant Power Switches Using CMOS Transistor Stacking | %1 | 0 | 5 months 6 days ago |
| Biblio | Analysis and Design of a SiGe BiCMOS PA for 6G FR3 Band With 29-dBm P SAT and 40.1% PAE | %1 | 0 | 6 months 1 week ago |
| Biblio | Analysis of Hybrid Dual-Path Step-Down Topology for High-Frequency, Integrated Dc-Dc Converters | %1 | 0 | 6 months 1 week ago |
| Biblio | A 5.1–10.5 GHz SiGe BiCMOS Power Amplifier for 6GNR with 29 dBm PSAT and 40.1% PAE | %1 | 0 | 6 months 2 weeks ago |
| Biblio | Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers | %1 | 0 | 6 months 2 weeks ago |
| Biblio | Analysis of CMRR in Doubly-Tuned Transformer Baluns | %1 | 0 | 1 year 2 months ago |
| Biblio | On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers | %1 | 0 | 1 year 2 months ago |
| Biblio | On the Optimal Design of Integrated AC-DC Converters for Energy Harvesting | %1 | 0 | 1 year 2 months ago |
| Biblio | A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies | %1 | 0 | 1 year 3 months ago |
| Biblio | A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs | %1 | 0 | 1 year 3 months ago |
| Biblio | On the Benefits of the Common-Mode Resonance on the 1/f ² Phase Noise Sideband | %1 | 0 | 1 year 3 months ago |
| Biblio | Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology | %1 | 0 | 1 year 7 months ago |
| Biblio | On the Efficiency of Output-Matched Radiofrequency Power Amplifiers | %1 | 0 | 1 year 7 months ago |