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Export 136 results:
Author Title Type [ Year(Asc)]
2018
A. Passamani, Ponton, D., Wolter, A., Knoblinger, G., and Bevilacqua, A., A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm2 Area w/ 2D Digital-Pre-Distortion and Package Combiner, in 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018.
P. Scaramuzza, Rubino, C., Caruso, M., Tiebout, M., Bevilacqua, A., and Neviani, A., Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp. 3780 - 3789, 2018.
A. Franceschin, Padovan, F., Nonis, R., and Bevilacqua, A., On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, pp. 657 - 661, 2018.
F. Padovan, Quadrelli, F., Bassi, M., Tiebout, M., and Bevilacqua, A., A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations, in 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018.
F. Pepe, Bevilacqua, A., and Andreani, P., On the Remarkable Performance of the Series-Resonance CMOS Oscillator, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, pp. 531-542, 2018.
A. Mazzanti and Bevilacqua, A., Second-Order Equivalent Circuits for the Design of Doubly-Tuned Transformer Matching Networks, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 12, pp. 4157 - 4168, 2018.
2016
F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation, IEEE Journal of Solid-State Circuits, vol. 51, pp. 1525-1536, 2016.
F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers, in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 363-366.
S. Brenna, Padovan, F., Neviani, A., Bevilacqua, A., Bonfanti, A., and Lacaita, A. L., A 64-Channel 965-uW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, pp. 528-532, 2016.
A. Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., Analysis and design of power and efficiency in third-order matching networks for switched-capacitor power-amplifiers, Analog Integrated Circuits and Signal Processing, vol. 89, no. 2, pp. 307-315, 2016.
A. Celin and Gerosa, A., A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 702-705.
G. Spiazzi, Marconi, S., and Bevilacqua, A., Step-Up DC-DC converters combining basic topologies with charge pump, in 2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL), 2016, pp. 1-6.

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