| Title | A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs |
| Publication Type | Conference Paper |
| Year of Publication | 2024 |
| Authors | Grimaldi, L, Iesurum, A, Boi, G, Versolatto, F, Steffan, G, Padovan, F, Koltsov, H, Bevilacqua, A, Cherniak, D |
| Conference Name | 2024 IEEE European Solid-State Electronics Research Conference (ESSERC) |
| Keywords | CMOS, Digital Phase-locked loops (DPLLs), digital pre-distortion, digitally-controlled oscillator (DCO), fast locking, Frequency modulation, frequency synthesizers, Jitter, mm-Wave, Phase modulation, Power demand, Prototypes, Spread spectrum communication, Standards, Time-frequency analysis, Transient analysis, Wireless communication |
| DOI | 10.1109/ESSERC62670.2024.10719534 |