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Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology

TitleAnalysis of a Split-Constant-Slope Digital-to-Time Converter Topology
Publication TypeConference Paper
Year of Publication2024
AuthorsZugno, N, Bevilacqua, A
Conference Name2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME)
KeywordsCMOS technology, constant slope, controlled delay, Digital-to-time converter (DTC), Fractional-N PLL, integral non-linearity (INL), Modulation, Robustness, Semiconductor device modeling, Sensitivity, Silicon-on-insulator, Topology
DOI10.1109/PRIME61930.2024.10559739