You are here

Biblio

Export 202 results:

Author Title Type [ Year

]

2026

D. Frassetto, Cabizza, S., Zilio, N. ', Karim, A., Garbossa, C., Agostinelli, M., Spiazzi, G., Bevilacqua, A., and Neviani, A., “A Highly Integrated Dual-Path Step-Down Hybrid DC–DC Converter With Self-Balanced Flying Capacitor and Reduced Inductor Current”, IEEE Open Journal of Power Electronics, vol. 7, pp. 167-179, 2026.

2025

L. Navarin, Norling, K., Parenzan, M., Uran, A., Ruzzu, S., Rathinam, K., Neviani, A., and Bevilacqua, A., “A 0.13-μm HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication”, IEEE Journal of Solid-State Circuits, pp. 1-12, 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., “A 0.7 V Multi-Class Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22 nm CMOS”, IEEE Solid-State Circuits Letters, vol. 8, pp. 217 - 220, 2025.

D. Pecile, Kokorovic, S., Gambarucci, A., and Bevilacqua, A., “A 5.1–10.5 GHz SiGe BiCMOS Power Amplifier for 6GNR with 29 dBm PSAT and 40.1% PAE”, in 2025 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2025.

D. Pecile, Pollin, A., Dal Maistro, D., Gambarucci, A., De Astis, G., and Bevilacqua, A., “A 5-7 GHz BiCMOS Front-End Module for WiFi 6e with 2.2 dB NF and 16 dBm PAVG at −40 dB EVM”, in 2025 20th European Microwave Integrated Circuits Conference (EuMIC), 2025.

L. Navarin, Norling, K., Parenzan, M., Uran, A., Ruzzu, S., Rathinam, K., Neviani, A., and Bevilacqua, A., “A 5.75mW Fully-Integrated Galvanic Isolator for Gate Drivers with Asynchronous 66.7/66.7 Mb/s Full-Duplex Communication”, in 2025 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2025.

D. Frassetto, Cabizza, S., Karim, A., Spiazzi, G., Bevilacqua, A., and Neviani, A., “Accurate Analysis of Switching Transients in the High-Frequency, Integrated Dual-Path Step-Down DC-DC Converter”, in 2025 IEEE Nordic Circuits and Systems Conference (NorCAS), 2025.

D. Pecile, Gambarucci, A., Kokorovic, S., and Bevilacqua, A., “Analysis and Design of a SiGe BiCMOS PA for 6G FR3 Band With 29-dBm P SAT and 40.1% PAE”, IEEE Transactions on Microwave Theory and Techniques, pp. 1-12, 2025.

L. Guglielmini and Bevilacqua, A., “Analysis of a gm-C Complex Filter for Low Power Wireless Receivers”, in 2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., “Analysis of a Three-Way Voltage-Mode Digital Doherty Power Amplifier for Bluetooth Applications”, in 2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2025.

D. Frassetto, Cabizza, S., Agostinelli, M., Garbossa, C., Spiazzi, G., Bevilacqua, A., and Neviani, A., “Analysis of Hybrid Dual-Path Step-Down Topology for High-Frequency, Integrated Dc-Dc Converters”, in 2025 International Conference on IC Design and Technology (ICICDT), 2025.

L. Navarin, Neviani, A., and Bevilacqua, A., “A DLL-Based FSK Demodulator for Asynchronous Communications”, in 2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2025.

L. Bellemo, Neviani, A., and Bevilacqua, A., “A Driving Methodology for Four-Quadrant Power Switches Using CMOS Transistor Stacking”, in 2025 23rd IEEE Interregional NEWCAS Conference (NEWCAS), 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., “Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-9, 2025.

L. Navarin, Norling, K., Parenzan, M., Ruzzu, S., Neviani, A., and Bevilacqua, A., “A Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication”, IEEE Solid-State Circuits Letters, vol. 8, pp. 289-292, 2025.

D. Pecile, Gambarrucci, A., Kokorovic, S., and Bevilacqua, A., “A Study of the Efficiency of Output-Matched Radiofrequency Power Amplifiers”, Analog Integrated Circuits and Signal Processing, vol. 125, no. 3, p. 42, 2025.

A. Bevilacqua and Mazzanti, A., “On the Upconversion of the Cross-Coupled Pair 1/f Noise Into Phase Noise in Current-Biased Class-B CMOS Oscillators”, IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 1-10, 2025.

2024

L. Grimaldi, Iesurum, A., Boi, G., Versolatto, F., Steffan, G., Padovan, F., Koltsov, H., Bevilacqua, A., and Cherniak, D., “A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs”, in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.

A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs”, IEEE Journal of Solid-State Circuits, vol. 59, pp. 294-306, 2024.

L. Tomasin, Vogrig, D., Neviani, A., and Bevilacqua, A., “Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters”, IEEE Transactions on Microwave Theory and Techniques, vol. 72, pp. 2840-2851, 2024.

N. Zugno and Bevilacqua, A., “Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology”, in 2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2024.

A. Bevilacqua and Mazzanti, A., “Analysis of CMRR in Doubly-Tuned Transformer Baluns”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, pp. 4874-4878, 2024.

L. Bellemo and Bevilacqua, A., “On the Benefits of the Common-Mode Resonance on the 1/f ² Phase Noise Sideband”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, pp. 3715-3719, 2024.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., “On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers”, in 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024.

D. Pecile, Kokorovic, S., Gambarucci, A., and Bevilacqua, A., “On the Efficiency of Output-Matched Radiofrequency Power Amplifiers”, in 2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2024.

Pages