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2025

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., “A 0.7 V Multi-Class Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22 nm CMOS”, IEEE Solid-State Circuits Letters, vol. 8, pp. 217 - 220, 2025.

L. Navarin, Norling, K., Parenzan, M., Uran, A., Ruzzu, S., Rathinam, K., Neviani, A., and Bevilacqua, A., “A 5.75mW Fully-Integrated Galvanic Isolator for Gate Drivers with Asynchronous 66.7/66.7 Mb/s Full-Duplex Communication”, in 2025 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2025.

D. Frassetto, Cabizza, S., Karim, A., Spiazzi, G., Bevilacqua, A., and Neviani, A., “Accurate Analysis of Switching Transients in the High-Frequency, Integrated Dual-Path Step-Down DC-DC Converter”, in 2025 IEEE Nordic Circuits and Systems Conference (NorCAS), 2025.

D. Frassetto, Cabizza, S., Agostinelli, M., Garbossa, C., Spiazzi, G., Bevilacqua, A., and Neviani, A., “Analysis of Hybrid Dual-Path Step-Down Topology for High-Frequency, Integrated Dc-Dc Converters”, in 2025 International Conference on IC Design and Technology (ICICDT), 2025.

L. Navarin, Neviani, A., and Bevilacqua, A., “A DLL-Based FSK Demodulator for Asynchronous Communications”, in 2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2025.

2024

L. Grimaldi, Iesurum, A., Boi, G., Versolatto, F., Steffan, G., Padovan, F., Koltsov, H., Bevilacqua, A., and Cherniak, D., “A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs”, in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.

A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs”, IEEE Journal of Solid-State Circuits, vol. 59, pp. 294-306, 2024.

2019

M. Bassi, Boi, G., Padovan, F., Fritzin, J., Di Martino, S., Knauder, D., and Bevilacqua, A., “A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS”, IEEE Solid-State Circuits Letters, vol. 2, pp. 107-110, 2019.

2017

D. Vogrig, Bevilacqua, A., Gerosa, A., and Neviani, A., “A Symbol-Duty-Cycled 440-pJ/b Impulse Radio Receiver With 0.57-aJ Sensitivity in 130-nm CMOS”, IEEE Transactions on Microwave Theory and Techniques, vol. 65, pp. 565-573, 2017.

2015

M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., “A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 413-422, 2015.

2013

M. Bassi, Caruso, M., Bevilacqua, A., and Neviani, A., “A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer”, IEEE Journal of Solid-State Circuits, vol. 48, pp. 1741-1750, 2013.

2010

A. Bevilacqua, Lorenzon, L., Da Dalt, N., Gerosa, A., and Neviani, A., “A 4.1 to 5.1 GHz 430 uA injection-locked frequency divider by 7 in 65 nm CMOS”, in Proceedings of the ESSCIRC 2010, 2010, pp. 150 -153.

2009

S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., “A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS”, in Proceedings of ESSCIRC 2009, 2009, pp. 444 -447.

2008

A. Gerosa, Costa, M. D., Bevilacqua, A., Vogrig, D., and Neviani, A., “An energy-detector for non-coherent impulse-radio UWB receivers”, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008, 2008, pp. 2705 -2708.

2007

A. Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., “An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS”, in Proc. of IEEE 2007 European Solid State Circuits Conference, 2007, pp. 139 -142.

2001

A. Gerosa, Novo, A., Mengalli, A., and Neviani, A., “A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker”, in Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 2001, vol. 1, pp. 296 -299 vol. 1.