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2025

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., “A 0.7 V Multi-Class Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22 nm CMOS”, IEEE Solid-State Circuits Letters, vol. 8, pp. 217 - 220, 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., “Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-9, 2025.

L. Navarin, Norling, K., Parenzan, M., Ruzzu, S., Neviani, A., and Bevilacqua, A., “A Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication”, IEEE Solid-State Circuits Letters, vol. 8, pp. 289-292, 2025.

2024

L. Tomasin, Vogrig, D., Neviani, A., and Bevilacqua, A., “Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters”, IEEE Transactions on Microwave Theory and Techniques, vol. 72, pp. 2840-2851, 2024.

N. Zugno and Bevilacqua, A., “Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology”, in 2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2024.

2016

A. Celin and Gerosa, A., “A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior”, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 702-705.

2015

A. Celin and Gerosa, A., “Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs”, in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 1454-1457.