You are here
Biblio
Export 9 results:
Author Title Type [ Year
] Filters: Author is Bevilacqua, A. and Keyword is CMOS analogue integrated circuits [Clear All Filters]
, “A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS”, IEEE Solid-State Circuits Letters, vol. 2, pp. 107-110, 2019.
, “Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs”, in Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC), 2015, 2015, pp. 1-4.
, “A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP”, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 179-182.
, “A linear model of efficiency for Switched-Capacitor RF Power-Amplifiers”, in 2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2014, pp. 1-4.
, “A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request”, in Proceedings of the ESSCIRC 2010, 2010, pp. 498 -501.
, “A 0.13 um CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers”, in Digest of Technical Papers of 2007 IEEE International Solid-State Circuits Conference, 2007, pp. 420 -612.
, “An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS”, in Proc. of IEEE 2007 European Solid State Circuits Conference, 2007, pp. 139 -142.
, “A low-voltage III-order log-domain filter in standard CMOS technology with tunable frequency”, in 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06. , 2006, pp. 90 -93.
, “An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers”, in Digest of Technical Papers of 2004 IEEE International Solid-State Circuits Conference, 2004, pp. 382 - 533 Vol.1.