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2025

L. Navarin, Norling, K., Parenzan, M., Uran, A., Ruzzu, S., Rathinam, K., Neviani, A., and Bevilacqua, A., “A 0.13-μm HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication”, IEEE Journal of Solid-State Circuits, pp. 1-12, 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., “A 0.7 V Multi-Class Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22 nm CMOS”, IEEE Solid-State Circuits Letters, vol. 8, pp. 217 - 220, 2025.

D. Pecile, Kokorovic, S., Gambarucci, A., and Bevilacqua, A., “A 5.1–10.5 GHz SiGe BiCMOS Power Amplifier for 6GNR with 29 dBm PSAT and 40.1% PAE”, in 2025 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2025.

D. Pecile, Pollin, A., Dal Maistro, D., Gambarucci, A., De Astis, G., and Bevilacqua, A., “A 5-7 GHz BiCMOS Front-End Module for WiFi 6e with 2.2 dB NF and 16 dBm PAVG at −40 dB EVM”, in 2025 20th European Microwave Integrated Circuits Conference (EuMIC), 2025.

D. Pecile, Pollin, A., Dal Maistro, D., Gambarucci, A., De Astis, G., and Bevilacqua, A., “A 5-7 GHz BiCMOS Front-End Module for WiFi 6e with 2.2 dB NF and 16 dBm PAVG at −40 dB EVM”, in 2025 20th European Microwave Integrated Circuits Conference (EuMIC), 2025.

L. Navarin, Norling, K., Parenzan, M., Uran, A., Ruzzu, S., Rathinam, K., Neviani, A., and Bevilacqua, A., “A 5.75mW Fully-Integrated Galvanic Isolator for Gate Drivers with Asynchronous 66.7/66.7 Mb/s Full-Duplex Communication”, in 2025 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2025.

D. Pecile, Gambarucci, A., Kokorovic, S., and Bevilacqua, A., “Analysis and Design of a SiGe BiCMOS PA for 6G FR3 Band With 29-dBm P SAT and 40.1% PAE”, IEEE Transactions on Microwave Theory and Techniques, pp. 1-12, 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., “Analysis of a Three-Way Voltage-Mode Digital Doherty Power Amplifier for Bluetooth Applications”, in 2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2025.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., “Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp. 1-9, 2025.

L. Navarin, Norling, K., Parenzan, M., Ruzzu, S., Neviani, A., and Bevilacqua, A., “A Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous 100/167 Mb/s ASK/FSK Full-Duplex Communication”, IEEE Solid-State Circuits Letters, vol. 8, pp. 289-292, 2025.

D. Pecile, Gambarrucci, A., Kokorovic, S., and Bevilacqua, A., “A Study of the Efficiency of Output-Matched Radiofrequency Power Amplifiers”, Analog Integrated Circuits and Signal Processing, vol. 125, no. 3, p. 42, 2025.

2024

L. Grimaldi, Iesurum, A., Boi, G., Versolatto, F., Steffan, G., Padovan, F., Koltsov, H., Bevilacqua, A., and Cherniak, D., “A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs”, in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.

A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs”, IEEE Journal of Solid-State Circuits, vol. 59, pp. 294-306, 2024.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., “On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers”, in 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024.

D. Pecile, Kokorovic, S., Gambarucci, A., and Bevilacqua, A., “On the Efficiency of Output-Matched Radiofrequency Power Amplifiers”, in 2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2024.

2023

D. Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, pp. 607-617, 2023.

2022

L. Tomasin, Andreani, P., Boi, G., Padovan, F., and Bevilacqua, A., “A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise”, IEEE Journal of Solid-State Circuits, vol. 57, pp. 2802-2811, 2022.

A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS”, in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022.

F. Quadrelli, Manente, D., Seebacher, D., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications”, IEEE Journal of Solid-State Circuits, vol. 57, pp. 1968-1981, 2022.

N. Modolo, De Santi, C., Baratella, G., Bettini, A., Borga, M., Posthuma, N., Bakeroot, B., You, S., Decoutere, S., Bevilacqua, A., Neviani, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., “Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices”, IEEE Transactions on Electron Devices, pp. 1-6, 2022.

2021

L. Tomasin, Boi, G., Padovan, F., and Bevilacqua, A., “A 10.7–14.1 GHz Reconfigurable Octacore DCO with −126 dBc/Hz Phase Noise at 1 MHz offset in 28 nm CMOS”, in 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2021.

A. Franceschin, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A 20-GHz Class-C VCO With 80-GHz Fourth-Harmonic Output in 28-nm CMOS”, IEEE Microwave and Wireless Components Letters, vol. 31, pp. 1154-1157, 2021.

D. Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A 22–31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS”, in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021.

2020

A. Franceschin, Andreani, P., Padovan, F., Bassi, M., and Bevilacqua, A., “A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects”, IEEE Journal of Solid-State Circuits, vol. 55, pp. 1842-1853, 2020.

D. Manente, Padovan, F., Seebacher, D., Bassi, M., and Bevilacqua, A., “A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P1dB in 28-nm Bulk CMOS”, IEEE Solid-State Circuits Letters, vol. 3, pp. 170-173, 2020.

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