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Biblio
] , “A 0.7 V Multi-Class Digital Doherty Power Amplifier for BLE Applications With 41% Peak DE in 22 nm CMOS”, IEEE Solid-State Circuits Letters, vol. 8, pp. 217 - 220, 2025.
, “A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters”, in Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on, 1999, pp. 195 -198.