You are here
Biblio
2024
L. Grimaldi, Iesurum, A., Boi, G., Versolatto, F., Steffan, G., Padovan, F., Koltsov, H., Bevilacqua, A., and Cherniak, D.,
“A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs”, in
2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.