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Biblio
2025
L. Navarin, Norling, K., Parenzan, M., Uran, A., Ruzzu, S., Rathinam, K., Neviani, A., and Bevilacqua, A.,
“A 0.13-μm HV CMOS Fully-Integrated Galvanic Isolator for Gate Drivers With Asynchronous Full-Duplex Communication”,
IEEE Journal of Solid-State Circuits, pp. 1-12, 2025.
D. Frassetto, Cabizza, S., Karim, A., Spiazzi, G., Bevilacqua, A., and Neviani, A.,
“Accurate Analysis of Switching Transients in the High-Frequency, Integrated Dual-Path Step-Down DC-DC Converter”, in
2025 IEEE Nordic Circuits and Systems Conference (NorCAS), 2025.
2024
L. Grimaldi, Iesurum, A., Boi, G., Versolatto, F., Steffan, G., Padovan, F., Koltsov, H., Bevilacqua, A., and Cherniak, D.,
“A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs”, in
2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.