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Biblio
] , “A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs”, in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.
, “A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise”, IEEE Journal of Solid-State Circuits, vol. 57, pp. 2802-2811, 2022.
, “A 10.7–14.1 GHz Reconfigurable Octacore DCO with −126 dBc/Hz Phase Noise at 1 MHz offset in 28 nm CMOS”, in 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2021.