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CTH08-3: Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code

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TitleCTH08-3: Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code
Publication TypeConference Paper
Year of Publication2006
AuthorsGraell i Amat, A, Vogrig, D, Benedetto, S, Montorsi, G, Neviani, A, Gerosa, A
Conference NameGlobal Telecommunications Conference, 2006. GLOBECOM '06. IEEE
Keywordsanalog iterative decoder, analog memory, block length, code rate, concatenated codes, convolutional codes, interleaved codes, iterative decoding, performance mismatch impact, reconfigurable analog decoder, reconfigurable interleaver, serially concatenated convolutional code, single-input single-output, SISO decoder, trellis code, trellis codes
DOI10.1109/GLOCOM.2006.77
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