| Title | Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code |
| Publication Type | Journal Article |
| Year of Publication | 2006 |
| Authors | Graell i Amat, A, Benedetto, S, Montorsi, G, Vogrig, D, Neviani, A, Gerosa, A |
| Journal | Communications, IEEE Transactions on |
| Volume | 54 |
| Pagination | 1973 -1982 |
| ISSN | 0090-6778 |
| Keywords | 0.35 micron, 3.3 V, 3G mobile communication, bit-error rate, block length-40 UMTS turbo code, circuit transient behavior, CMOS analog decoder, CMOS analogue integrated circuits, component mismatch, decoding, discrete time systems, discrete-time first-order model, error statistics, fast BER simulation, integrated circuit design, integrated circuit testing, Third Generation Partnership Project standard, transistor-level simulation, turbo codes, universal mobile telecommunications system |
| DOI | 10.1109/TCOMM.2006.884836 |
| Full Text | |