The pioneering work of Loeliger's and Hagenauer's groups led to the first successful implementations of analog iterative decoders in BiCMOS technology, and demonstrated the potential of this approach over the digital approach in terms of maximum attainable speed and power efficiency. Since then, the research efforts aimed at moving from the proof-of-concept design toward real-world applications have multiplied. The first step was to move from a bipolar to a more attractive full CMOS implementation, though still for a very simple Hamming (8,4) code. Shortly after, Gaudet et al. realized the first analog turbo decoder, which is a significant step ahead with respect to a decoder for a single convolutional code, but still far from a real application due to the limited interleaver size (16 bit).
Within this context we have designed, implemented, and successfully tested the first reported analog turbo decoder for a realistic application, a parallel concatenated, rate 1/3, code defined in the 3GPP standard with interleaver size of 40 bits and a codeword size of 132 bits.
The prototypes realized so far have shown an outstanding improvement in the power efficiency with respect to their digital counterparts, with a varying (from one implementation to the other) yet limited error-correcting performance loss. A further research effort is necessary to demonstrate that analog decoders for very high performance codes are feasible and maintain their superiority over the digital implementation. Turbo codes and low-density parity-check codes can get very close to the unconstrained Shannon limit for error correction provided that the data block length is large enough (in the range of thousands of bits). Modern data communications standards require block length and code rate programmability. The main research issue is then to demonstrate that it possible to design and realize power-efficient analog decoders with large and reconfigurable block length, programmable code rate and data throughput of hundreds of Mb/s (in CMOS technology) or several Gb/s (in BiCMOS technology).
Analog Turbo Decoding for UMTS ChannelWe have prototyped an analog decoder for the 40-bit block length, rate 1/3, Turbo Code defined in the UMTS standard. This is a significant step ahead in the evolution of analog decoders from simple proof-of-concept prototypes towards real world applications. The prototype is fully integrated in a three-metal, double-poly, 0.35 µm CMOS technology, and includes an I/O interface that maximizes the decoder throughput. After the successful implementation of proof-of-concept analog iterative decoders by different research groups both in bipolar and CMOS technologies, this is the first reported prototype of analog decoder for a realistic error-correcting code. The decoder was successfully tested at the maximum data rate defined in the standard (2 Mbit/s), with an overall power consumption of 10.3 mW at 3.3 V, going down to 7.6 mW with the decoder core operated at 2 V, and an extremely low energy per decoded bit and trellis state (0.85 nJ for the decoder core alone).
Collaborations
Integrated Circuits for Biomedical Applications
| A fully-integrated CMOS cardiac pacemaker |
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Implantable biomedical devices can benefit from design solutions in submicron CMOS technologies, since the high level of integration can significantly help in reducing the implanted device size, especially if design techniques that avoid off-chip components are used. Furthermore low-power techniques for the design of CMOS circuits can be profitably exploited in order to reduce the system power consumption, which is one of the main goals for biomedical devices. It is also worth to consider that often these systems lay in the category of low-voltage applications, because they are battery operated and are supposed to work correctly even when the battery discharges from its initial value to the end-of-life (EOL) voltage. This activity is based on this approach, and led to the integration in a pure CMOS technology of the analog blocks of a cardiac pacemaker. The system includes a dual chamber sensing stage that allows to amplify, filter and digitize both the atrial and the ventricular spontaneous cardiac activity, properly sensed by the pacemaker catheters. In addition the system includes a cuople of voltage multipliers in order to generate the volatge pulse to stimulate the heart. The realized circuit makes extensive use of current-mode translinear circuits, with particular emphasis on Log-domain circuits. The CMOS implementations of these circuits have indeed demonstrated a good power efficiency and are well suited for low-voltage environments. A power-optimized Sigma-Delta A/D converter has been realized for signal digitization, because the chance to use a digital version of the acquired signal allows more advanced pacing strategies. As a result of the used design approach, the realized system can operate with a supply voltage from 2.8V down to 1.8V, which is about 200mV below the typical EOL voltage of a lithium-iodine battery, commonly used in pacemakers. More importantly the total current consumption of the whole chip is fully compatible with the available power budget in cardiac pacemakers. Therefore the realized system gives a realistic contribution to full integration of the pacemaker on a single CMOS chip. This work has also demonstrated how established low-power and low-voltage design techniques for CMOS circuits can be profitably exploited in order to improve performance in a biomedical system like the cardiac pacemaker. |
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