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Conference Paper
M. Camponeschi, Bevilacqua, A., Neviani, A., and Andreani, P., Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 2063 -2066.
A. Xotta, Vogrig, D., Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., Bruccoleri, M., and Betti, G., An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels, in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, 2002, vol. 5, p. V-69 - V-72 vol.5.
M. PERENZONI, Gerosa, A., and Neviani, A., Analog CMOS Implementation of Gallager’s Interative Decoding algorithm applied to a Block Turbo Code, in ISCAS, 2003, vol. 5, pp. 813–816.
S. Soldà, Vogrig, D., Bevilacqua, A., Gerosa, A., and Neviani, A., Analog decoding of trellis coded modulation for multi-level flash memories, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008., 2008, pp. 744 -747.
A. Gerosa, Novo, A., and Neviani, A., An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process, in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 152 -157.
A. Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS, in Proc. of IEEE 2007 European Solid State Circuits Conference, 2007, pp. 139 -142.
A. G. I. Amatt, Benedetto, S., Montorsi, G., Vogrig, D., Neviani, A., and Gerosa, A., An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code, in Communications, 2005. ICC 2005. 2005 IEEE International Conference on, 2005, vol. 1, pp. 663 - 667 Vol. 1.
A. Graell i Amat, Montorsi, G., Benedetto, S., Vogrig, D., Neviani, A., and Gerosa, A., An analog turbo decoder for the UMTS standard, in Information Theory, 2004. ISIT 2004. Proceedings. International Symposium on, 2004, p. 296.
A. Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs, in Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC), 2015, 2015, pp. 1-4.
M. Camponeschi, Bevilacqua, A., and Andreani, P., Analysis and design of a low-power single-stage CMOS wireless receiver, in Proc. of 2009 NORCHIP, 2009, pp. 1 -4.