Biblio

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2016
Celin, A., and A. Gerosa, "A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior", 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 702-705, May, 2016.
Brenna, S., F. Padovan, A. Neviani, A. Bevilacqua, A. Bonfanti, and A. L. Lacaita, "A 64-Channel 965-uW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 6, pp. 528-532, June, 2016.
2015
Celin, A., and A. Gerosa, "Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs", 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1454-1457, May, 2015.
2008
2007
Bevilacqua, A., C. Sandner, A. Gerosa, and A. Neviani, "Quadrature VCOs Based on Coupled PLLs", IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, pp. 2140 -2143, 2007.
Bevilacqua, A., F. P. Pavan, C. Sandner, A. Gerosa, and A. Neviani, "Transformer-Based Dual-Mode Voltage-Controlled Oscillators", IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 4, pp. 293 -297, 2007.