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Integrated Circuits for Analog and RF µ-Systems
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2015
M. Bassi
,
Zhao, J.
,
Bevilacqua, A.
,
Ghilioni, A.
,
Mazzanti, A.
, and
Svelto, F.
,
“
A 40-67 GHz Power Amplifier With 13 dBm PSAT and 16% PAE in 28 nm CMOS LP
”
,
IEEE Journal of Solid-State Circuits
, vol. 50, pp. 1618-1628, 2015.
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2019
M. Bassi
,
Boi, G.
,
Padovan, F.
,
Fritzin, J.
,
Di Martino, S.
,
Knauder, D.
, and
Bevilacqua, A.
,
“
A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS
”
,
IEEE Solid-State Circuits Letters
, vol. 2, pp. 107-110, 2019.
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2014
A. Bevilacqua
and
Neviani, A.
,
“
Energy-efficient ultra-wideband impulse radios for short-range low-data rate communications
”
, in
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)
, 2014, pp. 874-877.
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2016
S. Brenna
,
Padovan, F.
,
Neviani, A.
,
Bevilacqua, A.
,
Bonfanti, A.
, and
Lacaita, A. L.
,
“
A 64-Channel 965-uW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS
”
,
IEEE Transactions on Circuits and Systems II: Express Briefs
, vol. 63, pp. 528-532, 2016.
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2018
A. Mazzanti
and
Bevilacqua, A.
,
“
Second-Order Equivalent Circuits for the Design of Doubly-Tuned Transformer Matching Networks
”
,
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 65, no. 12, pp. 4157 - 4168, 2018.
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2014
F. Padovan
,
Bevilacqua, A.
, and
Neviani, A.
,
“
A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS
”
, in
European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th
, 2014, pp. 287-290.
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J. Zhao
,
Bassi, M.
,
Bevilacqua, A.
,
Ghilioni, A.
,
Mazzanti, A.
, and
Svelto, F.
,
“
A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP
”
, in
European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th
, 2014, pp. 179-182.
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Recent Publications
Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs
On the Benefits of the Common-Mode Resonance On the 1/f2 Phase Noise Sideband
A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies
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