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2024

A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs”, IEEE Journal of Solid-State Circuits, vol. 59, pp. 294-306, 2024.

L. Tomasin, Vogrig, D., Neviani, A., and Bevilacqua, A., “Analysis and Design of Reactive Passive Mixers for High-Order Modulation IoT Cartesian Transmitters”, IEEE Transactions on Microwave Theory and Techniques, vol. 72, pp. 2840-2851, 2024.

N. Zugno and Bevilacqua, A., “Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology”, in 2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2024.

A. Bevilacqua and Mazzanti, A., “Analysis of CMRR in Doubly-Tuned Transformer Baluns”, IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1-1, 2024.

L. Bellemo and Bevilacqua, A., “On the Benefits of the Common-Mode Resonance on the 1/f ² Phase Noise Sideband”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, pp. 3715-3719, 2024.

D. Pecile, Kokorovic, S., Gambarucci, A., and Bevilacqua, A., “On the Efficiency of Output-Matched Radiofrequency Power Amplifiers”, in 2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2024.

L. Tomasin, Iesurum, A., Gobbo, A., Neviani, A., and Bevilacqua, A., “A Stacking Technique for High-Swing Low-Phase Noise Class-C Oscillators Using Core Devices in Ultrascaled CMOS Technologies”, IEEE Transactions on Circuits and Systems II: Express Briefs, pp. 1-1, 2024.

2023

F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., “A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner”, IEEE Journal of Solid-State Circuits, vol. 58, pp. 634-646, 2023.

D. Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, pp. 607-617, 2023.

N. Zugno, Brandonisio, F., Niederfriniger, T., and Bevilacqua, A., “On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies”, in 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2023.

L. Tomasin, Vogrig, D., Neviani, A., and Bevilacqua, A., “A Reactive Passive Mixer for 16-QAM Cartesian IoT Transmitters in 22 nm FD-SOI CMOS”, in 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2023.

L. Tomasin and Bevilacqua, A., “A Time-Variant Analysis of Passive Resistive Mixers Using Thevenin Theorem”, in 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2023.

2022

L. Tomasin, Andreani, P., Boi, G., Padovan, F., and Bevilacqua, A., “A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise”, IEEE Journal of Solid-State Circuits, vol. 57, pp. 2802-2811, 2022.

A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS”, in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022.

S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., “A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching”, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.

F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., “A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler”, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.

A. Bettini, Cosnier, T., Magnani, A., Syshchyk, O., Borga, M., Decoutere, S., and Neviani, A., “Analysis and Design of a Fully-Integrated Pulsed LiDAR Driver in 100V-GaN IC Technology”, in 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2022.

F. Quadrelli, Manente, D., Seebacher, D., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications”, IEEE Journal of Solid-State Circuits, vol. 57, pp. 1968-1981, 2022.

N. Modolo, De Santi, C., Baratella, G., Bettini, A., Borga, M., Posthuma, N., Bakeroot, B., You, S., Decoutere, S., Bevilacqua, A., Neviani, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., “Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices”, IEEE Transactions on Electron Devices, pp. 1-6, 2022.

S. M. Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., “A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μ s-Locking-Time”, IEEE Journal of Solid-State Circuits, pp. 1-14, 2022.

C. Shi, Song, M., Gao, Z., Bevilacqua, A., Dolmans, G., and Liu, Y. - H., “Galvanic-Coupled Trans-Dural Data Transfer for High-Bandwidth Intracortical Neural Sensing”, IEEE Transactions on Microwave Theory and Techniques, vol. 70, pp. 4579-4589, 2022.

F. Chiocchetta, De Santi, C., Rampazzo, F., Mukherjee, K., Grünenpütt, J., Sommer, D., Blanck, H., Lambert, B., Gerosa, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., “GaN RF HEMT Reliability: Impact of Device Processing on I-V Curve Stability and Current Collapse”, in 2022 IEEE International Reliability Physics Symposium (IRPS), 2022.

2021

L. Tomasin, Boi, G., Padovan, F., and Bevilacqua, A., “A 10.7–14.1 GHz Reconfigurable Octacore DCO with −126 dBc/Hz Phase Noise at 1 MHz offset in 28 nm CMOS”, in 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2021.

A. Franceschin, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A 20-GHz Class-C VCO With 80-GHz Fourth-Harmonic Output in 28-nm CMOS”, IEEE Microwave and Wireless Components Letters, vol. 31, pp. 1154-1157, 2021.

D. Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A 22–31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS”, in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021.

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