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C
A. Celin and Gerosa, A., A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 702-705.
M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 413-422, 2015.
M. Caruso, Bevilacqua, A., and Neviani, A., An X-Band Lumped-Element Wilkinson Combiner With Embedded Impedance Transformation, IEEE Microwave and Wireless Components Letters, vol. 24, pp. 689-691, 2014.
M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., Wideband {2–16GHz} local oscillator generation for short-range radar applications, in Proceedings of the 2013 ESSCIRC, 2013, pp. 49-52.
M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., A 2-16GHz 204mW 3mm-Resolution Stepped Frequency Radar for Breast Cancer Diagnostic Imaging in 65nm CMOS, in IEEE ISSCC Digest of Technical Papers, 2013, pp. 204-241.
A. D. Capobianco, Khan, M. S., Caruso, M., and Bevilacqua, A., 3-18 GHz compact planar antenna for short-range radar imaging, Electronics Letters, vol. 50, pp. 1016-1018, 2014.
M. Camponeschi, Bevilacqua, A., Tiebout, M., and Neviani, A., A X-Band I/Q Upconverter in 65 nm CMOS for High Resolution FMCW Radars, IEEE Microwave and Wireless Components Letters, vol. 22, pp. 141 -143, 2012.
M. Camponeschi, Bevilacqua, A., Neviani, A., and Andreani, P., Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 2063 -2066.
M. Camponeschi, Bevilacqua, A., and Andreani, P., Analysis and design of a low-power single-stage CMOS wireless receiver, in Proc. of 2009 NORCHIP, 2009, pp. 1 -4.
M. Camponeschi, Bevilacqua, A., and Andreani, P., Time-variant analysis and design of a power efficient ISM-band quadrature receiver, Analog Integrated Circuits and Signal Processing, vol. 67, pp. 11-20, 2011.
B
F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.
F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner, IEEE Journal of Solid-State Circuits, vol. 58, pp. 634-646, 2023.
S. Brenna, Padovan, F., Neviani, A., Bevilacqua, A., Bonfanti, A., and Lacaita, A. L., A 64-Channel 965-uW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, pp. 528-532, 2016.
F. Boscolo, Padovan, F., Quadrelli, F., Tiebout, M., Neviani, A., and Bevilacqua, A., A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 91-94.
J. Borremans, Bevilacqua, A., Bronckers, S., Dehan, M., Kuijk, M., Wambacq, P., and Craninckx, J., A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2693 -2705, 2008.
A. Bilato, Issakov, V., and Bevilacqua, A., A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.
A. Bilato, Issakov, V., and Bevilacqua, A., Considerations on 120GHz LO Signal Generation and Distribution for Highly-Integrated Multi-Channel Radar Transceivers, in 2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), 2019.
A. Bilato, Issakov, V., Mazzanti, A., and Bevilacqua, A., A Multichannel D-Band Radar Receiver With Optimized LO Distribution, IEEE Solid-State Circuits Letters, vol. 4, pp. 141-144, 2021.
A. Bevilacqua, Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., A 6-9-GHz programmable gain LNA with integrated balun in 90-nm CMOS, in IEEE International Conference on Ultra-Wideband, 2008. ICUWB 2008. , 2008, vol. 1, pp. 25 -28.
A. Bevilacqua and Andreani, P., An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 59, pp. 938 -945, 2012.
A. Bevilacqua and Niknejad, A. M., An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers, in Digest of Technical Papers of 2004 IEEE International Solid-State Circuits Conference, 2004, pp. 382 - 533 Vol.1.
A. Bevilacqua and Andreani, P., On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory, in 2011 IEEE International Symposium on Circuits and Systems (ISCAS), 2011, pp. 217 -220.
A. Bevilacqua, Sandner, C., Gerosa, A., and Neviani, A., A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers, IEEE Microwave and Wireless Components Letters, vol. 16, pp. 134 -136, 2006.
A. Bevilacqua, Great lessons from the back of the envelope, IEEE Solid-State Circuits Magazine, vol. 6, pp. 45-45, 2014.
A. Bevilacqua, Lorenzon, L., Da Dalt, N., Gerosa, A., and Neviani, A., A 4.1 to 5.1 GHz 430 uA injection-locked frequency divider by 7 in 65 nm CMOS, in Proceedings of the ESSCIRC 2010, 2010, pp. 150 -153.

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