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A. Novo, Gerosa, A., and Neviani, A., A Sub-Micron CMOS Programmable Charge Pump for Implantable Pacemaker, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, vol. 27, pp. 211–217, 2001.
A. Novo, Gerosa, A., Neviani, A., Zanoni, E., and Mozzi, A., Programmable voltage multipliers for pacemaker output pulse generation in CMOS 0.8 um technology, in Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European, 1999, pp. 386 - 389.
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D. Oloumi, Bevilacqua, A., and Bassi, M., UWB Radar for High Resolution Breast Cancer Scanning: System, Architectures, and Challenges, in 2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), 2019.
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F. Padovan, Tiebout, M., Mertens, K., Bevilacqua, A., and Neviani, A., A SiGe bipolar VCO for backhaul E-band communication systems, in Proceedings of the 2012 ESSCIRC, 2012, pp. 402 -405.
F. Padovan, Bevilacqua, A., and Neviani, A., A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 287-290.
F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation, IEEE Journal of Solid-State Circuits, vol. 51, pp. 1525-1536, 2016.
F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation, in European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st, 2015, pp. 56-59.
F. Padovan, Quadrelli, F., Bassi, M., Tiebout, M., and Bevilacqua, A., A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations, in 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018.
F. Padovan, Tiebout, M., Mertens, K. L. R., Bevilacqua, A., and Neviani, A., Design of Low-Noise K -Band SiGe Bipolar VCOs: Theory and Implementation, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 607-615, 2015.
F. Padovan, Tiebout, M., Dielacher, F., Bevilacqua, A., and Neviani, A., SiGe BiCMOS VCO with 27% tuning range for 5G communications, in 2015 Asia-Pacific Microwave Conference (APMC), 2015, vol. 1, pp. 1-3.
F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers, in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 363-366.
F. Padovan, Tiebout, M., Mertens, K., Bevilacqua, A., and Neviani, A., A K-band SiGe bipolar VCO with transformer-coupled varactor for backhaul links, in 2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF),, 2013, pp. 108-110.
A. Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs, in Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC), 2015, 2015, pp. 1-4.
A. Passamani, Ponton, D., Wolter, A., Knoblinger, G., and Bevilacqua, A., A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm2 Area w/ 2D Digital-Pre-Distortion and Package Combiner, in 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018.
A. Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., A linear model of efficiency for Switched-Capacitor RF Power-Amplifiers, in 2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2014, pp. 1-4.
A. Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., Analysis and design of power and efficiency in third-order matching networks for switched-capacitor power-amplifiers, Analog Integrated Circuits and Signal Processing, vol. 89, no. 2, pp. 307-315, 2016.
A. Passamani, Ponton, D., Thaller, E., Knoblinger, G., Neviani, A., and Bevilacqua, A., A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE, in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 232-233.
F. Pepe, Bevilacqua, A., and Andreani, P., On the Remarkable Performance of the Series-Resonance CMOS Oscillator, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, pp. 531-542, 2018.
M. PERENZONI, Gerosa, A., and Neviani, A., Analog CMOS Implementation of Gallager’s Interative Decoding algorithm applied to a Block Turbo Code, in ISCAS, 2003, vol. 5, pp. 813–816.

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