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Journal Article
S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., A 0.06 mm2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS, IEEE Journal of Solid-State Circuits, vol. 45, pp. 1295 -1304, 2010.
D. Vogrig, Gerosa, A., Neviani, A., Amat, A. G., Montorsi, G., and Benedetto, S., A 0.35- mu;m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code, Solid-State Circuits, IEEE Journal of, vol. 40, pp. 753 - 762, 2005.
F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation, IEEE Journal of Solid-State Circuits, vol. 51, pp. 1525-1536, 2016.
L. Tomasin, Andreani, P., Boi, G., Padovan, F., and Bevilacqua, A., A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise, IEEE Journal of Solid-State Circuits, vol. 57, pp. 2802-2811, 2022.
A. Gatti, Spiazzi, G., Gerosa, A., Neviani, A., and Bevilacqua, A., A 130-nm CMOS Dual Input-Polarity DC–DC Converter for Low-Power Applications, IEEE Solid-State Circuits Letters, vol. 2, pp. 211-214, 2019.
A. Gerosa and Neviani, A., A 1.8uW Sigma-Delta Modulator for 8-bit Digitization of Cardiac Signals in Implantable Pacemakers Operating Down to 1.8V, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS, vol. 52, pp. 71–76, 2005.
A. Franceschin, Andreani, P., Padovan, F., Bassi, M., and Bevilacqua, A., A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects, IEEE Journal of Solid-State Circuits, vol. 55, pp. 1842-1853, 2020.
A. Franceschin, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., A 20-GHz Class-C VCO With 80-GHz Fourth-Harmonic Output in 28-nm CMOS, IEEE Microwave and Wireless Components Letters, vol. 31, pp. 1154-1157, 2021.
M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 413-422, 2015.
A. Bevilacqua and Andreani, P., A 2.7–6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, pp. 1–10, 2012.
D. Manente, Padovan, F., Seebacher, D., Bassi, M., and Bevilacqua, A., A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P1dB in 28-nm Bulk CMOS, IEEE Solid-State Circuits Letters, vol. 3, pp. 170-173, 2020.
A. Gerosa, Cortelazzo, G. M., Baschirotto, A., and Malavasi, E., 2D video rate SC FIR filters based on analog RAMs, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 46, pp. 1348 -1360, 1999.
A. D. Capobianco, Khan, M. S., Caruso, M., and Bevilacqua, A., 3-18 GHz compact planar antenna for short-range radar imaging, Electronics Letters, vol. 50, pp. 1016-1018, 2014.
M. Bassi, Boi, G., Padovan, F., Fritzin, J., Di Martino, S., Knauder, D., and Bevilacqua, A., A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS, IEEE Solid-State Circuits Letters, vol. 2, pp. 107-110, 2019.
M. Bassi, Zhao, J., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., A 40-67 GHz Power Amplifier With 13 dBm PSAT and 16% PAE in 28 nm CMOS LP, IEEE Journal of Solid-State Circuits, vol. 50, pp. 1618-1628, 2015.
S. Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13um CMOS, IEEE Journal of Solid-State Circuits, vol. 46, pp. 1636 -1647, 2011.
S. Brenna, Padovan, F., Neviani, A., Bevilacqua, A., Bonfanti, A., and Lacaita, A. L., A 64-Channel 965-uW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, pp. 528-532, 2016.
M. Bassi, Caruso, M., Bevilacqua, A., and Neviani, A., A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer, IEEE Journal of Solid-State Circuits, vol. 48, pp. 1741-1750, 2013.
F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner, IEEE Journal of Solid-State Circuits, vol. 58, pp. 634-646, 2023.
A. Gerosa, Xotta, A., Bevilacqua, A., and Neviani, A., An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Σ Δ Modulator and a Flash Converter, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, pp. 2109 -2124, 2006.
S. Veni, Andreani, P., Caruso, M., Tiebout, M., and Bevilacqua, A., Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO, IEEE Journal of Solid-State Circuits, vol. 55, pp. 2345-2355, 2020.
A. Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems, IEEE Journal of Solid-State Circuits, vol. 44, pp. 331 -343, 2009.

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