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Conference Paper
A. Bevilacqua and Svelto, F., Non-linear spectral analysis of direct conversion wireless receivers, in IEEE 2002 Radio and Wireless Conference, 2002, pp. 39 - 42.
A. Gerosa, Neviani, A., Xotta, A., and Mian, G. A., A novel architecture to reduce complexity in hard disk read channel based on fractionally spaced equalization, in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, 2001, vol. 2, pp. 1099 -1102 vol.2.
A. Gerosa, Bevilacqua, A., Neviani, A., and Xotta, A., An optimal architecture for a multimode ADC, based on the cascade of a Sigma-Delta modulator and a flash converter, in Proceedings of 2006 IEEE International Symposium on Circuits and Systems, 2006, p. 4 pp.
A. Celin and Gerosa, A., Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs, in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 1454-1457.
G. Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
A. Gerosa, Neviani, A., and Cortelazzo, G. M., A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters, in Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on, 1999, pp. 195 -198.
A. Maniero, Gerosa, A., and Neviani, A., Performance Optimization in Micro-Power, Low-Voltage, Log-Domain Filters in Pure CMOS Technology, in ISCAS, 2003, vol. 1, pp. 565–568.
A. Novo, Gerosa, A., Neviani, A., Zanoni, E., and Mozzi, A., Programmable voltage multipliers for pacemaker output pulse generation in CMOS 0.8 um technology, in Solid-State Circuits Conference, 1999. ESSCIRC '99. Proceedings of the 25th European, 1999, pp. 386 - 389.
A. Xotta, Gerosa, A., and Neviani, A., A Programmable-Order Sigma-Delta Converter for a Multi-Standard Wireless Receiver, in WowCas, Vancouver B.C., Canada, 2004, vol. 1, pp. 33–34.
F. Padovan, Quadrelli, F., Bassi, M., Tiebout, M., and Bevilacqua, A., A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations, in 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018.
A. Bevilacqua, Sandner, C., Gerosa, A., and Neviani, A., Quadrature VCOs Based on Coupled PLLs, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 2140 -2143.
L. Tomasin, Vogrig, D., Neviani, A., and Bevilacqua, A., A Reactive Passive Mixer for 16-QAM Cartesian IoT Transmitters in 22 nm FD-SOI CMOS, in 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2023.
A. Gerosa, A ready-to-use design procedure for operational transconductance amplifiers that minimizes power consumption, in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, 2001, vol. 2, pp. 949 -952 vol.2.
A. Celin and Gerosa, A., A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 702-705.
A. Gerosa, Neviani, A., and Zanoni, E., A SC Video Filter with Analog-RAM-based Delay Efficient Realization, in ECCTD, 1999, vol. 2, pp. 1247–1250.
C. Fantozzi, Vangelista, L., Vogrig, D., and Campana, O., SDR implementation of a DVB-T2 transmitter: The core building blocks, in 2011 IEEE International Conference on Consumer Electronics (ICCE), 2011, pp. 391 -392.
F. Padovan, Tiebout, M., Dielacher, F., Bevilacqua, A., and Neviani, A., SiGe BiCMOS VCO with 27% tuning range for 5G communications, in 2015 Asia-Pacific Microwave Conference (APMC), 2015, vol. 1, pp. 1-3.
F. Padovan, Tiebout, M., Mertens, K., Bevilacqua, A., and Neviani, A., A SiGe bipolar VCO for backhaul E-band communication systems, in Proceedings of the 2012 ESSCIRC, 2012, pp. 402 -405.
A. Gerosa, RUBIN, R., and Neviani, A., A Simplified Analysis of Noise in Switched Capacitor Networks from a Circuit Design Perspective, in ECCTD, 2001, vol. 1, pp. 261–264.
G. Spiazzi, Marconi, S., and Bevilacqua, A., Step-Up DC-DC converters combining basic topologies with charge pump, in 2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL), 2016, pp. 1-6.
D. Vogrig, Bevilacqua, A., Gerosa, A., and Neviani, A., A symbol-duty-cycled 440 pJ/b impulse radio receiver with 0.57 aJ sensitivity in 130 nm CMOS, in Radio Frequency Integrated Circuits Symposium (RFIC), 2015 IEEE, 2015, pp. 243-246.
S. Dal Toso, Bevilacqua, A., Gerosa, A., and Neviani, A., A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 1903 -1906.
L. Tomasin and Bevilacqua, A., A Time-Variant Analysis of Passive Resistive Mixers Using Thevenin Theorem, in 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2023.
A. Bevilacqua and Niknejad, A. M., An ultra-wideband CMOS LNA for 3.1 to 10.6 GHz wireless receivers, in Digest of Technical Papers of 2004 IEEE International Solid-State Circuits Conference, 2004, pp. 382 - 533 Vol.1.
S. D. Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking, in Digest of Technical Papers of 2008 IEEE International Solid-State Circuits Conference, 2008, pp. 124 -601.

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