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A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS”, in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022.

G

A. Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., SOLDA, S., Neviani, A., and Gerosa, A., “Iterative Analog Decoder for a SCCC”, in Analog Decoding Workshop, 2006.

A. Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., Neviani, A., and Gerosa, A., “CTH08-3: Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code”, in Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE, 2006, pp. 1 -6.

A. Graell i Amat, Montorsi, G., Benedetto, S., Vogrig, D., Neviani, A., and Gerosa, A., “An analog turbo decoder for the UMTS standard”, in Information Theory, 2004. ISIT 2004. Proceedings. International Symposium on, 2004, p. 296.

A. Graell i Amat, Benedetto, S., Montorsi, G., Vogrig, D., Neviani, A., and Gerosa, A., “Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code”, Communications, IEEE Transactions on, vol. 54, pp. 1973 -1982, 2006.

A. Gerosa and Neviani, A., “A LOW-POWER DECIMATION FILTER FOR A SIGMA-DELTA CONVERTER BASED ON A POWER-OPTMIZED SINC FILTER”, in ISCAS, 2004, vol. 2, pp. 245–248.

A. Gerosa and Neviani, A., “A Very Low-Power 8-bit Sigma-Delta Converter in a 0.8um CMOS Technology for the Sensing Chain of a Cardiac Pacemaker, Operating down to 1.8V”, in ISCAS, 2003, vol. 5, pp. 49–52.

A. Gerosa, Maniero, A., and Neviani, A., “A Fully-Integrated Dual-Channel Log-Domain Programmable Preamplifier and Filter for an Implantable Cardiac Pacemakers”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, vol. 51, pp. 1916–1925, 2004.

A. Gerosa, Soldà, S., Bevilacqua, A., Vogrig, D., and Neviani, A., “An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, pp. 1030 -1040, 2009.

A. Gerosa, Neviani, A., and Cortelazzo, G. M., “A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters”, in Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on, 1999, pp. 195 -198.

A. Gerosa, Xotta, A., Bevilacqua, A., and Neviani, A., “An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Σ Δ Modulator and a Flash Converter”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, pp. 2109 -2124, 2006.

A. Gerosa, “Design of Power-Optimized OTAs for SC Applications”. 2001.

A. Gerosa and Neviani, A., “Enhancing Output Voltage Swing in Low-Voltage Micro-Power OTA Using Self-Cascode”, ELECTRONICS LETTERS, vol. 39, pp. 638–639, 2003.

A. Gerosa, Soldà, S., Bevilacqua, A., Vogrig, D., and Neviani, A., “A digitally programmable ring oscillator in the UWB range”, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS),, 2010, pp. 1101 -1104.

A. Gerosa, Neviani, A., Xotta, A., and Mian, G. A., “A novel architecture to reduce complexity in hard disk read channel based on fractionally spaced equalization”, in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, 2001, vol. 2, pp. 1099 -1102 vol.2.

A. Gerosa, Cortelazzo, G. M., Baschirotto, A., and Malavasi, E., “2D video rate SC FIR filters based on analog RAMs”, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 46, pp. 1348 -1360, 1999.

A. Gerosa, Bevilacqua, A., and Spiazzi, G., “A Multi-Phase Self-Reconfigurable Switched-Capacitor DC-DC Step-Up Converter Integrated in CMOS Technology”, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019.

A. Gerosa, Neviani, A., and Maniero, A., “A Fully-Integrated Two-Channel A/D Interface for the Acquisition of Cardiac Signals in Implantable Pacemakers”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 39, pp. 1083–1093, 2004.

A. Gerosa, Costa, M. D., Bevilacqua, A., Vogrig, D., and Neviani, A., “An energy-detector for non-coherent impulse-radio UWB receivers”, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008, 2008, pp. 2705 -2708.

A. Gerosa, Novo, A., and Neviani, A., “An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process”, in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 152 -157.

A. Gerosa, Bevilacqua, A., Neviani, A., and Xotta, A., “An optimal architecture for a multimode ADC, based on the cascade of a Sigma-Delta modulator and a flash converter”, in Proceedings of 2006 IEEE International Symposium on Circuits and Systems, 2006, p. 4 pp.

A. Gerosa, Xotta, A., Neviani, A., and Mian, G. A., “Frequency Offset Compensation in Fractionally Spaced Equalization”, IEE PROCEEDINGS. CIRCUITS, DEVICES AND SYSTEMS, vol. 150, pp. 134–140, 2003.

A. Gerosa, Elettronica Digitale, Esercizi risolti. PADOVA: Edizioni Libreria Progetto, 2006, pp. 1–216.

A. Gerosa, Soldan, M., Bevilacqua, A., and Neviani, A., “A 0.18-um CMOS Squarer Circuit for a Non-Coherent UWB Receiver”, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 421 -424.

A. Gerosa, “A ready-to-use design procedure for operational transconductance amplifiers that minimizes power consumption”, in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, 2001, vol. 2, pp. 949 -952 vol.2.

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