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A. Gerosa, Neviani, A., and Maniero, A., “A Fully-Integrated Two-Channel A/D Interface for the Acquisition of Cardiac Signals in Implantable Pacemakers”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 39, pp. 1083–1093, 2004.

A. Gerosa, Costa, M. D., Bevilacqua, A., Vogrig, D., and Neviani, A., “An energy-detector for non-coherent impulse-radio UWB receivers”, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008, 2008, pp. 2705 -2708.

A. Gerosa, Novo, A., and Neviani, A., “An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process”, in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 152 -157.

A. Gerosa, Bevilacqua, A., Neviani, A., and Xotta, A., “An optimal architecture for a multimode ADC, based on the cascade of a Sigma-Delta modulator and a flash converter”, in Proceedings of 2006 IEEE International Symposium on Circuits and Systems, 2006, p. 4 pp.

A. Gerosa, Xotta, A., Neviani, A., and Mian, G. A., “Frequency Offset Compensation in Fractionally Spaced Equalization”, IEE PROCEEDINGS. CIRCUITS, DEVICES AND SYSTEMS, vol. 150, pp. 134–140, 2003.

A. Gerosa, Elettronica Digitale, Esercizi risolti. PADOVA: Edizioni Libreria Progetto, 2006, pp. 1–216.

A. Gerosa, Soldan, M., Bevilacqua, A., and Neviani, A., “A 0.18-um CMOS Squarer Circuit for a Non-Coherent UWB Receiver”, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 421 -424.

A. Gerosa, “A ready-to-use design procedure for operational transconductance amplifiers that minimizes power consumption”, in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, 2001, vol. 2, pp. 949 -952 vol.2.

A. Gerosa, Bernardini, R., and Pietri, S., “A Fully Integrated Chaotic System for the Generation of Truly Random Numbers”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I. FUNDAMENTAL THEORY AND APPLICATIONS, vol. 49, pp. 993–1000, 2002.

A. Gerosa, Elettronica Digitale, Esercizi Risolti. PADOVA – ITA: Libreria Progetto, 2004, pp. 1–161.

A. Gerosa, Bernardini, R., and Pietri, S., “A fully integrated 8-bit, 20 MHz, truly random numbers generator, based on a chaotic system”, in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 87 -92.

A. Gerosa, Neviani, A., and Zanoni, E., “A SC Video Filter with Analog-RAM-based Delay Efficient Realization”, in ECCTD, 1999, vol. 2, pp. 1247–1250.

A. Gerosa, Maniero, A., and Neviani, A., “A Fully-Integrated Two-Channel A/D Interface for the Acquisition of Cardiac Signals in Implantable Pacemakers”, in ESSCIRC, 2003, vol. 1, pp. 157–160.

A. Gerosa and Neviani, A., “A 1.8uW Sigma-Delta Modulator for 8-bit Digitization of Cardiac Signals in Implantable Pacemakers Operating Down to 1.8V”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS, vol. 52, pp. 71–76, 2005.

A. Gerosa, Novo, A., and Neviani, A., “Low-power sensing and digitization of cardiac signals based on sigma-delta conversion”, in Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on, 2000, pp. 216 - 218.

A. Gerosa and Mian, G. A., “A low complexity EPR-IV equalizer for hard disk read channels”, in Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on, 1999, vol. 2, pp. 1069 -1072 vol.2.

A. Gerosa, Novo, A., Mengalli, A., and Neviani, A., “A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker”, in Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 2001, vol. 1, pp. 296 -299 vol. 1.

A. Gerosa and Mian, G. A., “An Equalizer for Hard Disk Drive Channels, with Low Sensitivity to Sampling Phase Variation”, in EUSIPCO-98, 1998, vol. 1, pp. 483–486.

A. Gerosa, Bevilacqua, A., and Neviani, A., “A local oscillator for WCDMA band VII based on frequency multiplication”, Analog Integrated Circuits and Signal Processing, vol. 72, no. 1, 2012.

A. Gerosa, RUBIN, R., and Neviani, A., “A Simplified Analysis of Noise in Switched Capacitor Networks from a Circuit Design Perspective”, in ECCTD, 2001, vol. 1, pp. 261–264.

A. Gerosa and Neviani, A., “A LOW-POWER DECIMATION FILTER FOR A SIGMA-DELTA CONVERTER BASED ON A POWER-OPTMIZED SINC FILTER”, in ISCAS, 2004, vol. 2, pp. 245–248.

A. Gerosa and Neviani, A., “A Very Low-Power 8-bit Sigma-Delta Converter in a 0.8um CMOS Technology for the Sensing Chain of a Cardiac Pacemaker, Operating down to 1.8V”, in ISCAS, 2003, vol. 5, pp. 49–52.

A. Gerosa, Maniero, A., and Neviani, A., “A Fully-Integrated Dual-Channel Log-Domain Programmable Preamplifier and Filter for an Implantable Cardiac Pacemakers”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, vol. 51, pp. 1916–1925, 2004.

A. Gerosa, Soldà, S., Bevilacqua, A., Vogrig, D., and Neviani, A., “An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, pp. 1030 -1040, 2009.

A. Gerosa, Neviani, A., and Cortelazzo, G. M., “A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters”, in Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on, 1999, pp. 195 -198.

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