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C

M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., “A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 413-422, 2015.

A. Celin and Gerosa, A., “Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs”, in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 1454-1457.

A. Celin and Gerosa, A., “A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior”, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 702-705.

F. Chiocchetta, De Santi, C., Rampazzo, F., Mukherjee, K., Grünenpütt, J., Sommer, D., Blanck, H., Lambert, B., Gerosa, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., “GaN RF HEMT Reliability: Impact of Device Processing on I-V Curve Stability and Current Collapse”, in 2022 IEEE International Reliability Physics Symposium (IRPS), 2022.

G. M. Cortelazzo, Malavasi, E., Gerosa, A., and Neviani, A., “A New Structure for Video-Rate 2D SC FIR Filters”, in EUSIPCO-96, 1996, vol. 2, pp. 1307–1310.

D

S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., “An Integrated Divide-by-Two Direct Injection-Locking Frequency Divider for Bands S Through Ku”, IEEE Transactions on Microwave Theory and Techniques, vol. 58, pp. 1686 -1695, 2010.

S. Dal Toso, Bevilacqua, A., Tiebout, M., Marsili, S., Sandner, C., Gerosa, A., and Neviani, A., “UWB Fast-Hopping Frequency Generation Based on Sub-Harmonic Injection Locking”, IEEE Journal of Solid-State Circuits, vol. 43, pp. 2844 -2852, 2008.

S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., “A 0.06 mm2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS”, IEEE Journal of Solid-State Circuits, vol. 45, pp. 1295 -1304, 2010.

S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., “A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS”, in Proceedings of ESSCIRC 2009, 2009, pp. 444 -447.

S. Dal Toso, Bevilacqua, A., Gerosa, A., and Neviani, A., “A thorough analysis of the tank quality factor in LC oscillators with switched capacitor banks”, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 1903 -1906.

S. M. Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., “A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μ s-Locking-Time”, IEEE Journal of Solid-State Circuits, pp. 1-14, 2022.

S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., “A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching”, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.

F

C. Fantozzi, Vangelista, L., Vogrig, D., and Campana, O., “SDR implementation of a DVB-T2 transmitter: The core building blocks”, in 2011 IEEE International Conference on Consumer Electronics (ICCE), 2011, pp. 391 -392.

A. Franceschin, Padovan, F., Nonis, R., and Bevilacqua, A., “On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, pp. 657 - 661, 2018.

A. Franceschin, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A 20-GHz Class-C VCO With 80-GHz Fourth-Harmonic Output in 28-nm CMOS”, IEEE Microwave and Wireless Components Letters, vol. 31, pp. 1154-1157, 2021.

A. Franceschin, Andreani, P., Padovan, F., Bassi, M., Nonis, R., and Bevilacqua, A., “A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion”, in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019.

A. Franceschin, Andreani, P., Padovan, F., Bassi, M., and Bevilacqua, A., “A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects”, IEEE Journal of Solid-State Circuits, vol. 55, pp. 1842-1853, 2020.

G

A. Gatti, Spiazzi, G., Gerosa, A., Neviani, A., and Bevilacqua, A., “A 130-nm CMOS Dual Input-Polarity DC–DC Converter for Low-Power Applications”, IEEE Solid-State Circuits Letters, vol. 2, pp. 211-214, 2019.

A. Gerosa, Bevilacqua, A., and Spiazzi, G., “A Multi-Phase Self-Reconfigurable Switched-Capacitor DC-DC Step-Up Converter Integrated in CMOS Technology”, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019.

A. Gerosa, Novo, A., Mengalli, A., and Neviani, A., “A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker”, in Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 2001, vol. 1, pp. 296 -299 vol. 1.

A. Gerosa and Mian, G. A., “An Equalizer for Hard Disk Drive Channels, with Low Sensitivity to Sampling Phase Variation”, in EUSIPCO-98, 1998, vol. 1, pp. 483–486.

A. Gerosa, Bevilacqua, A., and Neviani, A., “A local oscillator for WCDMA band VII based on frequency multiplication”, Analog Integrated Circuits and Signal Processing, vol. 72, no. 1, 2012.

A. Gerosa, RUBIN, R., and Neviani, A., “A Simplified Analysis of Noise in Switched Capacitor Networks from a Circuit Design Perspective”, in ECCTD, 2001, vol. 1, pp. 261–264.

A. Gerosa and Neviani, A., “A LOW-POWER DECIMATION FILTER FOR A SIGMA-DELTA CONVERTER BASED ON A POWER-OPTMIZED SINC FILTER”, in ISCAS, 2004, vol. 2, pp. 245–248.

A. Gerosa and Neviani, A., “A Very Low-Power 8-bit Sigma-Delta Converter in a 0.8um CMOS Technology for the Sensing Chain of a Cardiac Pacemaker, Operating down to 1.8V”, in ISCAS, 2003, vol. 5, pp. 49–52.

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