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Conference Paper

A. Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., “A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO”, in Proceedings of the 32nd European Solid-State Circuits Conference, 2006, pp. 440 -443.

J. Zhao, Bassi, M., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., “A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP”, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 179-182.

A. Bevilacqua, Lorenzon, L., Da Dalt, N., Gerosa, A., and Neviani, A., “A 4.1 to 5.1 GHz 430 uA injection-locked frequency divider by 7 in 65 nm CMOS”, in Proceedings of the ESSCIRC 2010, 2010, pp. 150 -153.

L. Grimaldi, Iesurum, A., Boi, G., Versolatto, F., Steffan, G., Padovan, F., Koltsov, H., Bevilacqua, A., and Cherniak, D., “A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs”, in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.

D. Pecile, Kokorovic, S., Gambarucci, A., and Bevilacqua, A., “A 5.1–10.5 GHz SiGe BiCMOS Power Amplifier for 6GNR with 29 dBm PSAT and 40.1% PAE”, in 2025 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2025.

L. Navarin, Norling, K., Parenzan, M., Uran, A., Ruzzu, S., Rathinam, K., Neviani, A., and Bevilacqua, A., “A 5.75mW Fully-Integrated Galvanic Isolator for Gate Drivers with Asynchronous 66.7/66.7 Mb/s Full-Duplex Communication”, in 2025 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2025.

S. Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., “A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request”, in Proceedings of the ESSCIRC 2010, 2010, pp. 498 -501.

S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., “A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching”, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.

A. Bevilacqua, Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., “A 6-9-GHz programmable gain LNA with integrated balun in 90-nm CMOS”, in IEEE International Conference on Ultra-Wideband, 2008. ICUWB 2008. , 2008, vol. 1, pp. 25 -28.

F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., “A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler”, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.

M. Camponeschi, Bevilacqua, A., Neviani, A., and Andreani, P., “Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end”, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 2063 -2066.

A. Xotta, Vogrig, D., Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., Bruccoleri, M., and Betti, G., “An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels”, in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, 2002, vol. 5, p. V-69 - V-72 vol.5.

M. PERENZONI, Gerosa, A., and Neviani, A., “Analog CMOS Implementation of Gallager’s Interative Decoding algorithm applied to a Block Turbo Code”, in ISCAS, 2003, vol. 5, pp. 813–816.

S. Soldà, Vogrig, D., Bevilacqua, A., Gerosa, A., and Neviani, A., “Analog decoding of trellis coded modulation for multi-level flash memories”, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008., 2008, pp. 744 -747.

A. Gerosa, Novo, A., and Neviani, A., “An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process”, in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 152 -157.

A. Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., “An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS”, in Proc. of IEEE 2007 European Solid State Circuits Conference, 2007, pp. 139 -142.

A. G. I. Amatt, Benedetto, S., Montorsi, G., Vogrig, D., Neviani, A., and Gerosa, A., “An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code”, in Communications, 2005. ICC 2005. 2005 IEEE International Conference on, 2005, vol. 1, pp. 663 - 667 Vol. 1.

A. Graell i Amat, Montorsi, G., Benedetto, S., Vogrig, D., Neviani, A., and Gerosa, A., “An analog turbo decoder for the UMTS standard”, in Information Theory, 2004. ISIT 2004. Proceedings. International Symposium on, 2004, p. 296.

A. Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., “Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs”, in Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC), 2015, 2015, pp. 1-4.

A. Bettini, Cosnier, T., Magnani, A., Syshchyk, O., Borga, M., Decoutere, S., and Neviani, A., “Analysis and Design of a Fully-Integrated Pulsed LiDAR Driver in 100V-GaN IC Technology”, in 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2022.

M. Camponeschi, Bevilacqua, A., and Andreani, P., “Analysis and design of a low-power single-stage CMOS wireless receiver”, in Proc. of 2009 NORCHIP, 2009, pp. 1 -4.

L. Guglielmini and Bevilacqua, A., “Analysis of a gm-C Complex Filter for Low Power Wireless Receivers”, in 2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2025.

N. Zugno and Bevilacqua, A., “Analysis of a Split-Constant-Slope Digital-to-Time Converter Topology”, in 2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2024.

E. Baiesi Fietta, Seebacher, D., Ponton, D., and Bevilacqua, A., “Analysis of a Three-Way Voltage-Mode Digital Doherty Power Amplifier for Bluetooth Applications”, in 2025 20th International Conference on PhD Research in Microelectronics and Electronics (PRIME), 2025.

D. Frassetto, Cabizza, S., Agostinelli, M., Garbossa, C., Spiazzi, G., Bevilacqua, A., and Neviani, A., “Analysis of Hybrid Dual-Path Step-Down Topology for High-Frequency, Integrated Dc-Dc Converters”, in 2025 International Conference on IC Design and Technology (ICICDT), 2025.

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