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M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., “A 2-16GHz 204mW 3mm-Resolution Stepped Frequency Radar for Breast Cancer Diagnostic Imaging in 65nm CMOS”, in IEEE ISSCC Digest of Technical Papers, 2013, pp. 204-241.

F. Boscolo, Padovan, F., Quadrelli, F., Tiebout, M., Neviani, A., and Bevilacqua, A., “A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset”, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 91-94.

D. Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A 22–31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS”, in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021.

A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS”, in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022.

A. Bevilacqua and Andreani, P., “A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2”, in NORCHIP, 2011, 2011, pp. 1 -4.

A. Bevilacqua and Andreani, P., “A 2.7–6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2”, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, pp. 1–10, 2012.

D. Manente, Padovan, F., Seebacher, D., Bassi, M., and Bevilacqua, A., “A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P1dB in 28-nm Bulk CMOS”, IEEE Solid-State Circuits Letters, vol. 3, pp. 170-173, 2020.

A. Passamani, Ponton, D., Wolter, A., Knoblinger, G., and Bevilacqua, A., “A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm2 Area w/ 2D Digital-Pre-Distortion and Package Combiner”, in 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018.

A. Gerosa, Cortelazzo, G. M., Baschirotto, A., and Malavasi, E., “2D video rate SC FIR filters based on analog RAMs”, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 46, pp. 1348 -1360, 1999.

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A. D. Capobianco, Khan, M. S., Caruso, M., and Bevilacqua, A., “3-18 GHz compact planar antenna for short-range radar imaging”, Electronics Letters, vol. 50, pp. 1016-1018, 2014.

A. Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., “A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO”, in Proceedings of the 32nd European Solid-State Circuits Conference, 2006, pp. 440 -443.

M. Bassi, Boi, G., Padovan, F., Fritzin, J., Di Martino, S., Knauder, D., and Bevilacqua, A., “A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS”, IEEE Solid-State Circuits Letters, vol. 2, pp. 107-110, 2019.

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M. Bassi, Zhao, J., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., “A 40-67 GHz Power Amplifier With 13 dBm PSAT and 16% PAE in 28 nm CMOS LP”, IEEE Journal of Solid-State Circuits, vol. 50, pp. 1618-1628, 2015.

J. Zhao, Bassi, M., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., “A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP”, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 179-182.

A. Bevilacqua, Lorenzon, L., Da Dalt, N., Gerosa, A., and Neviani, A., “A 4.1 to 5.1 GHz 430 uA injection-locked frequency divider by 7 in 65 nm CMOS”, in Proceedings of the ESSCIRC 2010, 2010, pp. 150 -153.

L. Grimaldi, Iesurum, A., Boi, G., Versolatto, F., Steffan, G., Padovan, F., Koltsov, H., Bevilacqua, A., and Cherniak, D., “A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs”, in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.

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S. Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., “A 5 Mb/s UWB-IR Transceiver Front-End for Wireless Sensor Networks in 0.13um CMOS”, IEEE Journal of Solid-State Circuits, vol. 46, pp. 1636 -1647, 2011.

S. Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., “A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request”, in Proceedings of the ESSCIRC 2010, 2010, pp. 498 -501.

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S. Brenna, Padovan, F., Neviani, A., Bevilacqua, A., Bonfanti, A., and Lacaita, A. L., “A 64-Channel 965-uW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, pp. 528-532, 2016.

M. Bassi, Caruso, M., Bevilacqua, A., and Neviani, A., “A 65-nm CMOS 1.75-15 GHz Stepped Frequency Radar Receiver for Early Diagnosis of Breast Cancer”, IEEE Journal of Solid-State Circuits, vol. 48, pp. 1741-1750, 2013.

S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., “A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching”, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.

A. Bevilacqua, Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., “A 6-9-GHz programmable gain LNA with integrated balun in 90-nm CMOS”, in IEEE International Conference on Ultra-Wideband, 2008. ICUWB 2008. , 2008, vol. 1, pp. 25 -28.

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F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., “A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner”, IEEE Journal of Solid-State Circuits, vol. 58, pp. 634-646, 2023.

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F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., “A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler”, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.

A

M. Camponeschi, Bevilacqua, A., Neviani, A., and Andreani, P., “Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end”, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 2063 -2066.

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