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2022

S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., “A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching”, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.

F. Quadrelli, Manente, D., Seebacher, D., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications”, IEEE Journal of Solid-State Circuits, pp. 1-1, 2022.

2021

L. Tomasin, Boi, G., Padovan, F., and Bevilacqua, A., “A 10.7–14.1 GHz Reconfigurable Octacore DCO with −126 dBc/Hz Phase Noise at 1 MHz offset in 28 nm CMOS”, in 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2021.

A. Franceschin, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A 20-GHz Class-C VCO With 80-GHz Fourth-Harmonic Output in 28-nm CMOS”, IEEE Microwave and Wireless Components Letters, vol. 31, pp. 1154-1157, 2021.

D. Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A 22–31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS”, in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021.

A. Bevilacqua and Mazzanti, A., “Doubly-Tuned Transformer Networks: A Tutorial”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, pp. 550-555, 2021.

S. Veni, Caruso, M., Seebacher, D., Neviani, A., and Bevilacqua, A., “A Fully Integrated 28 GHz Class-J Doherty Power Amplifier in 130 nm BiCMOS”, in SMACD / PRIME 2021; International Conference on SMACD and 16th Conference on PRIME, 2021.

P. Andreani and Bevilacqua, A., “Harmonic Oscillators in CMOS—A Tutorial Overview”, IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 2-17, 2021.

A. Bilato, Issakov, V., Mazzanti, A., and Bevilacqua, A., “A Multichannel D-Band Radar Receiver With Optimized LO Distribution”, IEEE Solid-State Circuits Letters, vol. 4, pp. 141-144, 2021.

2020

A. Franceschin, Andreani, P., Padovan, F., Bassi, M., and Bevilacqua, A., “A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects”, IEEE Journal of Solid-State Circuits, vol. 55, pp. 1842-1853, 2020.

D. Manente, Padovan, F., Seebacher, D., Bassi, M., and Bevilacqua, A., “A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P1dB in 28-nm Bulk CMOS”, IEEE Solid-State Circuits Letters, vol. 3, pp. 170-173, 2020.

S. Veni, Andreani, P., Caruso, M., Tiebout, M., and Bevilacqua, A., “Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO”, IEEE Journal of Solid-State Circuits, vol. 55, pp. 2345-2355, 2020.

A. Bevilacqua, “Fundamentals of Integrated Transformers: From Principles to Applications”, IEEE Solid-State Circuits Magazine, vol. 12, pp. 86-100, 2020.

S. Marconi, Spiazzi, G., Bevilacqua, A., and Galvano, M., “A Novel Integrated Step-Up Hybrid Converter With Wide Conversion Ratio”, IEEE Transactions on Power Electronics, vol. 35, pp. 2764-2775, 2020.

G. Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., “Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters”, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.

G. Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., “A Reconfigurable Switched Capacitor DC–DC Converter With 1.9–6.3-V Input Voltage Range and 85% Peak Efficiency in 28-nm CMOS”, IEEE Solid-State Circuits Letters, vol. 3, pp. 106-109, 2020.

2019

A. Bilato, Issakov, V., and Bevilacqua, A., “A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS”, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.

A. Gatti, Spiazzi, G., Gerosa, A., Neviani, A., and Bevilacqua, A., “A 130-nm CMOS Dual Input-Polarity DC–DC Converter for Low-Power Applications”, IEEE Solid-State Circuits Letters, vol. 2, pp. 211-214, 2019.

S. Veni, Caruso, M., Tiebout, M., and Bevilacqua, A., “A 17 GHz All-npn Push-Pull Class-C VCO”, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.

F. Quadrelli, Panazzolo, F., Tiebout, M., Padovan, F., Bassi, M., and Bevilacqua, A., “A 18.2-29.3 GHz Colpitts VCOs bank with -119.5 dBc/Hz Phase Noise at 1 MHz Offset for 5G Communications”, in 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019.

A. Franceschin, Andreani, P., Padovan, F., Bassi, M., Nonis, R., and Bevilacqua, A., “A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion”, in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019.

M. Bassi, Boi, G., Padovan, F., Fritzin, J., Di Martino, S., Knauder, D., and Bevilacqua, A., “A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS”, IEEE Solid-State Circuits Letters, vol. 2, pp. 107-110, 2019.

A. Bilato, Issakov, V., and Bevilacqua, A., “Considerations on 120GHz LO Signal Generation and Distribution for Highly-Integrated Multi-Channel Radar Transceivers”, in 2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), 2019.

G. Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., “Global Optimization of Reconfigurable Switched Capacitor DC-DC Converters”, in 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019.

A. Gerosa, Bevilacqua, A., and Spiazzi, G., “A Multi-Phase Self-Reconfigurable Switched-Capacitor DC-DC Step-Up Converter Integrated in CMOS Technology”, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019.

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