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2018

P. Scaramuzza, Rubino, C., Caruso, M., Tiebout, M., Bevilacqua, A., and Neviani, A., “Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique”, IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 1-10, 2018.

G. Spiazzi, Biadene, D., Marconi, S., and Bevilacqua, A., “Non-isolated High Step-up DC-DC Converter with Minimum Switch Voltage Stress”, IEEE Transactions on Power Electronics, pp. 1-1, 2018.

A. Franceschin, Padovan, F., Nonis, R., and Bevilacqua, A., “On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, pp. 657 - 661, 2018.

F. Padovan, Quadrelli, F., Bassi, M., Tiebout, M., and Bevilacqua, A., “A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations”, in 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018.

F. Pepe, Bevilacqua, A., and Andreani, P., “On the Remarkable Performance of the Series-Resonance CMOS Oscillator”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, pp. 531-542, 2018.

A. Mazzanti and Bevilacqua, A., “Second-Order Equivalent Circuits for the Design of Doubly-Tuned Transformer Matching Networks”, IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 1-12, 2018.

2017

A. Passamani, Ponton, D., Thaller, E., Knoblinger, G., Neviani, A., and Bevilacqua, A., “A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE”, in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 232-233.

F. Boscolo, Padovan, F., Quadrelli, F., Tiebout, M., Neviani, A., and Bevilacqua, A., “A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset”, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 91-94.

P. Scaramuzza, Rubino, C., Tiebout, M., Caruso, M., Ortner, M., Neviani, A., and Bevilacqua, A., “Class-AB and class-J 22 dBm SiGe HBT PAs for X-band radar systems”, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 187-190.

G. Spiazzi, Biadene, D., Marconi, S., and Bevilacqua, A., “Non-isolated high step-up DC-DC converter with minimum switch voltage stress”, in 2017 IEEE Southern Power Electronics Conference (SPEC), 2017.

D. Vogrig, Bevilacqua, A., Gerosa, A., and Neviani, A., “A Symbol-Duty-Cycled 440-pJ/b Impulse Radio Receiver With 0.57-aJ Sensitivity in 130-nm CMOS”, IEEE Transactions on Microwave Theory and Techniques, vol. 65, pp. 565-573, 2017.

2016

F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., “A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation”, IEEE Journal of Solid-State Circuits, vol. 51, pp. 1525-1536, 2016.

F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., “A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers”, in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 363-366.

S. Brenna, Padovan, F., Neviani, A., Bevilacqua, A., Bonfanti, A., and Lacaita, A. L., “A 64-Channel 965-uW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, pp. 528-532, 2016.

A. Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., “Analysis and design of power and efficiency in third-order matching networks for switched-capacitor power-amplifiers”, Analog Integrated Circuits and Signal Processing, vol. 89, no. 2, pp. 307-315, 2016.

A. Celin and Gerosa, A., “A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior”, in 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016, pp. 702-705.

G. Spiazzi, Marconi, S., and Bevilacqua, A., “Step-Up DC-DC converters combining basic topologies with charge pump”, in 2016 IEEE 17th Workshop on Control and Modeling for Power Electronics (COMPEL), 2016, pp. 1-6.

2015

F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., “A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation”, in European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st, 2015, pp. 56-59.

M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., “A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 413-422, 2015.

M. Bassi, Zhao, J., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., “A 40-67 GHz Power Amplifier With 13 dBm PSAT and 16% PAE in 28 nm CMOS LP”, IEEE Journal of Solid-State Circuits, vol. 50, pp. 1618-1628, 2015.

A. Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., “Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs”, in Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC), 2015, 2015, pp. 1-4.

A. Bevilacqua, “CMOS UWB Transceivers for Short-Range Microwave Medical Imaging”, in Wireless transceiver circuits, Boca Raton: CRC Press, Taylor & Francis group, 2015, pp. 305–333.

F. Padovan, Tiebout, M., Mertens, K. L. R., Bevilacqua, A., and Neviani, A., “Design of Low-Noise K -Band SiGe Bipolar VCOs: Theory and Implementation”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 607-615, 2015.

A. Celin and Gerosa, A., “Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs”, in 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, pp. 1454-1457.

A. Mazzanti and Bevilacqua, A., “On the Phase Noise Performance of Transformer-Based CMOS Differential-Pair Harmonic Oscillators”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 2334-2341, 2015.

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