%0 Journal Article %J Communications, IEEE Transactions on %D 2006 %T Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code %A Graell i Amat, A. %A Benedetto, S. %A Montorsi, G. %A Vogrig, D. %A Neviani, A. %A Gerosa, A. %K 0.35 micron %K 3.3 V %K 3G mobile communication %K bit-error rate %K block length-40 UMTS turbo code %K circuit transient behavior %K CMOS analog decoder %K CMOS analogue integrated circuits %K component mismatch %K decoding %K discrete time systems %K discrete-time first-order model %K error statistics %K fast BER simulation %K integrated circuit design %K integrated circuit testing %K Third Generation Partnership Project standard %K transistor-level simulation %K turbo codes %K universal mobile telecommunications system %B Communications, IEEE Transactions on %V 54 %P 1973 -1982 %G eng %R 10.1109/TCOMM.2006.884836