%0 Conference Paper %B 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) %D 2023 %T A Reactive Passive Mixer for 16-QAM Cartesian IoT Transmitters in 22 nm FD-SOI CMOS %A Tomasin, Lorenzo %A Vogrig, Daniele %A Neviani, Andrea %A Bevilacqua, A. %B 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) %G eng %R 10.1109/RFIC54547.2023.10186126 %0 Journal Article %J IEEE Solid-State Circuits Letters %D 2020 %T A Reconfigurable Switched Capacitor DC–DC Converter With 1.9–6.3-V Input Voltage Range and 85% Peak Efficiency in 28-nm CMOS %A G. Marin %A K. Cherniak %A V. Subotskaya %A E. Bodano %A C. Sandner %A Bevilacqua, A. %B IEEE Solid-State Circuits Letters %V 3 %P 106-109 %G eng %0 Journal Article %J IEEE Transactions on Circuits and Systems I: Regular Papers %D 2018 %T On the Remarkable Performance of the Series-Resonance CMOS Oscillator %A F. Pepe %A Bevilacqua, A. %A Andreani, P. %K Harmonic analysis %K Impedance %K impulse sensitivity function (ISF) %K Inverters %K MOS devices %K oscillators %K phase noise %K Topology %B IEEE Transactions on Circuits and Systems I: Regular Papers %V 65 %P 531-542 %8 Feb %R 10.1109/TCSI.2017.2727283 %0 Conference Paper %B 2016 IEEE International Symposium on Circuits and Systems (ISCAS) %D 2016 %T A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior %A A. Celin %A Gerosa, A. %K algorithm ciclicity %K Algorithm design and analysis %K bidirectional data-weighted averaging algorithm %K CMOS digital integrated circuits %K CMOS technology %K Complexity theory %K DAC %K device mismatch %K digital to analog converters %K digital-analogue conversion %K Hardware %K hardware complexity %K integrated circuit modelling %K Mathematical model %K Modulation %K Multiplexing %K sigma-delta modulation %K sigma-delta modulators %K size 65 nm %K spurs immunity %K Standards %B 2016 IEEE International Symposium on Circuits and Systems (ISCAS) %P 702-705 %8 May %R 10.1109/ISCAS.2016.7527337 %0 Conference Paper %B Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on %D 2001 %T A ready-to-use design procedure for operational transconductance amplifiers that minimizes power consumption %A Gerosa, A. %K bias current %K circuit optimisation %K design equations %K design procedure %K electric current %K folded-cascode amplifier %K minimized power consumption %K network synthesis %K operational amplifiers %K operational transconductance amplifiers %K OTA design procedure %K OTA performance %K power optimized OTA %K switched capacitor networks %K switched capacitor stage %K transistor size %B Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on %V 2 %P 949 -952 vol.2 %R 10.1109/ICECS.2001.957630