%0 Journal Article %J IEEE Solid-State Circuits Letters %D 2019 %T A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS %A M. Bassi %A G. Boi %A F. Padovan %A J. Fritzin %A S. Di Martino %A D. Knauder %A Bevilacqua, A. %K 5G communication systems %K 5G mobile communication %K Bandwidth %K BiCMOS technologies %K bulk CMOS technology %K carrier signal generation %K CMOS %K CMOS analogue integrated circuits %K communication systems %K edge-combining concept %K field effect MMIC %K fifth generation (5G) %K frequency 39 GHz %K Frequency conversion %K Frequency measurement %K frequency multiplier %K frequency multipliers %K frequency tripler %K Harmonic analysis %K harmonic rejection %K harmonics suppression %K high harmonic rejection ratio %K injection locked oscillators %K low phase noise %K low spur level %K mm-waves %K MMIC frequency convertors %K multipoint injection-locked ring oscillator %K phase noise %K power 25.0 mW %K radar %K Ring oscillators %K robust rejection ratio %K single-stage polyphase filter %K size 28 nm %K tripler %K V %K voltage 0.9 V %B IEEE Solid-State Circuits Letters %V 2 %P 107-110 %8 Sep. %G eng %R 10.1109/LSSC.2019.2930198