%0 Journal Article %J IEEE Transactions on Circuits and Systems I: Regular Papers %D 2006 %T An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Σ Δ Modulator and a Flash Converter %A Gerosa, A. %A Xotta, A. %A Bevilacqua, A. %A Neviani, A. %K 18.9 mW %K 3G mobile communication %K 4 bit %K 4.6 mW %K 5.5 mW %K 7.4 mW %K analog-to-digital converter %K analogue-digital conversion %K behavioral simulations %K Bluetooth %K cellular radio %K double-sampling SigmaDelta modulator %K flash converter %K global system for mobile communications %K internal quantizer %K multimode wireless receivers %K radio receivers %K transistor-level simulations %K universal mobile telecommunications system %K wireless LAN %K wireless local area network %B IEEE Transactions on Circuits and Systems I: Regular Papers %V 53 %P 2109 -2124 %R 10.1109/TCSI.2006.883840 %0 Conference Paper %B Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on %D 2001 %T A fully integrated 8-bit, 20 MHz, truly random numbers generator, based on a chaotic system %A Gerosa, A. %A Bernardini, R. %A Pietri, S. %K 0.8 micron %K 20 MHz %K 50 mW %K 8 bit %K analogue-digital conversion %K ASIC %K chaos generators %K chaotic system %K circuit nonidealities %K CMOS integrated circuits %K CMOS process %K compact architecture %K fully integrated implementation %K mixed analogue-digital integrated circuits %K pipeline ADC %K pipeline processing %K post-layout simulations %K random number generation %K random numbers generator %K statistical independence %K uniform distribution %B Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on %P 87 -92 %R 10.1109/SSMSD.2001.914944 %0 Conference Paper %B Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on %D 1999 %T A low complexity EPR-IV equalizer for hard disk read channels %A Gerosa, A. %A Mian, G.A. %K 0.35 mum %K ADC accuracy %K analogue-digital conversion %K area consumption %K BRE %K circuit design %K circuit simulation %K CMOS integrated circuits %K complexity %K digital post-processing %K equalisers %K equalization performance %K FIR filters %K fractionally spaced equalization %K hard discs %K hard disk read channels %K low complexity EPR-IV equalizer %K memory architecture %K network synthesis %K power consumption %K sampled data %K sampled data circuits %K standard CMOS %K transistor level simulation %B Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on %V 2 %P 1069 -1072 vol.2 %R 10.1109/ICECS.1999.813418