%0 Conference Paper %B 2016 IEEE International Symposium on Circuits and Systems (ISCAS) %D 2016 %T A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior %A A. Celin %A Gerosa, A. %K algorithm ciclicity %K Algorithm design and analysis %K bidirectional data-weighted averaging algorithm %K CMOS digital integrated circuits %K CMOS technology %K Complexity theory %K DAC %K device mismatch %K digital to analog converters %K digital-analogue conversion %K Hardware %K hardware complexity %K integrated circuit modelling %K Mathematical model %K Modulation %K Multiplexing %K sigma-delta modulation %K sigma-delta modulators %K size 65 nm %K spurs immunity %K Standards %B 2016 IEEE International Symposium on Circuits and Systems (ISCAS) %P 702-705 %8 May %R 10.1109/ISCAS.2016.7527337 %0 Conference Paper %B 2015 IEEE International Symposium on Circuits and Systems (ISCAS) %D 2015 %T Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs %A A. Celin %A Gerosa, A. %K Algorithm design and analysis %K analog-to-digital converter %K Clocks %K CMOS digital integrated circuits %K CMOS integrated circuits %K CMOS technologies %K CMOS technology %K data weighted averaging %K DEM algorithms %K dynamic element matching algorithms %K hardware complexity %K Heuristic algorithms %K internal DAC %K logic design %K mismatch cancellation %K Modulation %K multibit sigma-delta ADC %K multibit ΣΔ ADC %K Noise %K optimal DWA design %K sigma-delta modulation %K sigma-delta modulator %K size 65 nm %K Timing %K ΣΔ modulator %B 2015 IEEE International Symposium on Circuits and Systems (ISCAS) %P 1454-1457 %8 May %R 10.1109/ISCAS.2015.7168918 %0 Conference Paper %B Proceedings of 2006 IEEE International Symposium on Circuits and Systems %D 2006 %T An optimal architecture for a multimode ADC, based on the cascade of a Sigma-Delta modulator and a flash converter %A Gerosa, A. %A Bevilacqua, A. %A Neviani, A. %A Xotta, A. %K 18.9 mW %K 3G mobile communication %K 4 bit %K 4.6 mW %K 5.5 mW %K 7.4 mW %K Bluetooth %K cellular radio %K flash converter %K GSM %K internal quantizer %K multimode ADC %K optimal architecture %K power consumption %K sigma-delta modulation %K sigma-delta modulator %K UMTS %K wireless LAN %K WLANa %B Proceedings of 2006 IEEE International Symposium on Circuits and Systems %P 4 pp. %R 10.1109/ISCAS.2006.1692653 %0 Conference Paper %B Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on %D 2001 %T An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process %A Gerosa, A. %A Novo, A. %A Neviani, A. %K 0.8 micron %K analog front-end %K analogue processing circuits %K band-pass filtering %K biomedical signal %K biquadratic filters %K cardiac pacemaker %K CMOS analogue integrated circuits %K CMOS process %K log-domain filter %K low-noise pre-amplifier %K low-power design %K low-power electronics %K pacemakers %K peak detection %K preamplifiers %K SC biquadratic cell %K sensing chain %K sigma-delta converter %K sigma-delta modulation %K switched capacitor filters %B Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on %P 152 -157 %R 10.1109/SSMSD.2001.914956 %0 Conference Paper %B Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on %D 2000 %T Low-power sensing and digitization of cardiac signals based on sigma-delta conversion %A Gerosa, A. %A Novo, A. %A Neviani, A. %K 0.8 micron %K 2 muW %K 2 V %K 50 to 150 Hz %K 8 kHz %K cardiac signals %K CMOS integrated circuits %K CMOS technology %K digitization %K dynamic range %K low-power circuits %K low-power electronics %K low-power sensing %K medical signal processing %K oversampled frequency %K oversampling conversion techniques %K pacemaker %K pacemakers %K power dissipation %K sigma-delta conversion %K sigma-delta modulation %K signal sampling %K switched networks %K switched op-amp technique %K third order modulator %B Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on %P 216 - 218 %R 10.1109/LPE.2000.155282