%0 Journal Article %J IEEE Transactions on Circuits and Systems II: Express Briefs %D 2016 %T A 64-Channel 965-uW Neural Recording SoC With UWB Wireless Transmission in 130-nm CMOS %A S. Brenna %A Padovan, F. %A Neviani, A. %A Bevilacqua, A. %A A. Bonfanti %A A. L. Lacaita %K 64-channel neural recording SoC %K analog front end %K Analog-digital conversion %K Bandwidth %K biomedical electronics %K biomedical telemetry %K bit rate 20 Mbit/s %K BMI %K Brain???machine interface (BMI) %K capacitors %K CMOS digital integrated circuits %K CMOS process %K efficiency 11.7 percent %K Electronics packaging %K implantable electronics %K inputreferred noise %K low-noise bandpass amplifier %K noise efficiency factor %K power 965 muW %K Power demand %K pulse position modulation %K pulse-position modulation ultrawideband transmitter %K radiotelemetry %K raw neural signal %K SAR analog-to-digital converter %K size 130 nm %K system-on-chip %K transmitters %K ultra wideband communication %K ultra-wideband (UWB) %K ultrawideband (UWB) %K UWB wireless transmission %K voltage 0.5 V %K voltage 5.6 V %K Wireless communication %K wireless neural recording systems %K wireless telemetry %K word length 10 bit %B IEEE Transactions on Circuits and Systems II: Express Briefs %V 63 %P 528-532 %8 June %G eng %R 10.1109/TCSII.2016.2530882 %0 Conference Paper %B 2016 IEEE International Symposium on Circuits and Systems (ISCAS) %D 2016 %T A reduced hardware complexity data-weighted averaging algorithm with no tonal behavior %A A. Celin %A Gerosa, A. %K algorithm ciclicity %K Algorithm design and analysis %K bidirectional data-weighted averaging algorithm %K CMOS digital integrated circuits %K CMOS technology %K Complexity theory %K DAC %K device mismatch %K digital to analog converters %K digital-analogue conversion %K Hardware %K hardware complexity %K integrated circuit modelling %K Mathematical model %K Modulation %K Multiplexing %K sigma-delta modulation %K sigma-delta modulators %K size 65 nm %K spurs immunity %K Standards %B 2016 IEEE International Symposium on Circuits and Systems (ISCAS) %P 702-705 %8 May %R 10.1109/ISCAS.2016.7527337 %0 Conference Paper %B 2015 IEEE International Symposium on Circuits and Systems (ISCAS) %D 2015 %T Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs %A A. Celin %A Gerosa, A. %K Algorithm design and analysis %K analog-to-digital converter %K Clocks %K CMOS digital integrated circuits %K CMOS integrated circuits %K CMOS technologies %K CMOS technology %K data weighted averaging %K DEM algorithms %K dynamic element matching algorithms %K hardware complexity %K Heuristic algorithms %K internal DAC %K logic design %K mismatch cancellation %K Modulation %K multibit sigma-delta ADC %K multibit ΣΔ ADC %K Noise %K optimal DWA design %K sigma-delta modulation %K sigma-delta modulator %K size 65 nm %K Timing %K ΣΔ modulator %B 2015 IEEE International Symposium on Circuits and Systems (ISCAS) %P 1454-1457 %8 May %R 10.1109/ISCAS.2015.7168918 %0 Conference Paper %B IEEE International Conference on Ultra-Wideband, 2008. ICUWB 2008. %D 2008 %T A 6-9-GHz programmable gain LNA with integrated balun in 90-nm CMOS %A Bevilacqua, A. %A Sandner, C. %A Tiebout, M. %A Gerosa, A. %A Neviani, A. %K baluns %K CMOS digital integrated circuits %K Europe %K field effect MMIC %K frequency 4.5 GHz to 11 GHz %K frequency 6 GHz to 9 GHz %K gain 12.5 dB %K integrated balun %K Japan %K low noise amplifiers %K low-noise amplifier %K microwave amplifiers %K noise figure 3.9 dB to 5.1 dB %K programmable gain LNA %K pure digital CMOS technology %K size 90 nm %K ultra wideband communication %K ultrawideband communications %K USA %K UWB communications %B IEEE International Conference on Ultra-Wideband, 2008. ICUWB 2008. %V 1 %P 25 -28 %R 10.1109/ICUWB.2008.4653277 %0 Journal Article %J IEEE Journal of Solid-State Circuits %D 2008 %T A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS %A Borremans, J. %A Bevilacqua, A. %A Bronckers, S. %A Dehan, M. %A Kuijk, M. %A Wambacq, P. %A Craninckx, J. %K 4-port oscillator %K CMOS digital integrated circuits %K compact wideband front-end %K digital CMOS %K downconversion %K frequency 10 GHz %K frequency 3.5 GHz %K frequency synthesis %K inductorless LNA %K inductors %K low noise amplifiers %K MMIC oscillators %K RF front-end design %K single-inductor dual-band VCO %K size 90 nm %K voltage 1.2 V %K voltage-controlled oscillators %B IEEE Journal of Solid-State Circuits %V 43 %P 2693 -2705 %R 10.1109/JSSC.2008.2004865 %0 Conference Paper %B IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007 %D 2007 %T Quadrature VCOs Based on Coupled PLLs %A Bevilacqua, A. %A Sandner, C. %A Gerosa, A. %A Neviani, A. %K 0.13 micron %K CMOS digital integrated circuits %K coupled PLL %K digital CMOS technology %K dual-mode quadrature VCO %K phase locked loops %K quadrature signal generation %K voltage-controlled oscillators %B IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007 %P 2140 -2143 %R 10.1109/ISCAS.2007.378596 %0 Journal Article %J IEEE Transactions on Circuits and Systems II: Express Briefs %D 2007 %T Transformer-Based Dual-Mode Voltage-Controlled Oscillators %A Bevilacqua, A. %A Pavan, F.P. %A Sandner, C. %A Gerosa, A. %A Neviani, A. %K 0.13 micron %K 1 to 8 mW %K 2.5D electromagnetic simulation %K 3.6 to 7.8 GHz %K Agilent Momentum %K CMOS digital integrated circuits %K digital CMOS technology %K dual-mode voltage-controlled oscillators %K frequency tuning techniques %K microwave oscillators %K MMIC oscillators %K one-port network %K quality factor %K reconfigurable architectures %K resonators %K transformer-based resonator %K transformers %K two-port network %K VCO %K voltage-controlled oscillators %K wide-band voltage-controlled oscillator %B IEEE Transactions on Circuits and Systems II: Express Briefs %V 54 %P 293 -297 %R 10.1109/TCSII.2006.889734