%0 Conference Paper %B 2015 IEEE International Symposium on Circuits and Systems (ISCAS) %D 2015 %T Optimal DWA design in scaled CMOS technologies for mismatch cancellation in multibit ΣΔ ADCs %A A. Celin %A Gerosa, A. %K Algorithm design and analysis %K analog-to-digital converter %K Clocks %K CMOS digital integrated circuits %K CMOS integrated circuits %K CMOS technologies %K CMOS technology %K data weighted averaging %K DEM algorithms %K dynamic element matching algorithms %K hardware complexity %K Heuristic algorithms %K internal DAC %K logic design %K mismatch cancellation %K Modulation %K multibit sigma-delta ADC %K multibit ΣΔ ADC %K Noise %K optimal DWA design %K sigma-delta modulation %K sigma-delta modulator %K size 65 nm %K Timing %K ΣΔ modulator %B 2015 IEEE International Symposium on Circuits and Systems (ISCAS) %P 1454-1457 %8 May %R 10.1109/ISCAS.2015.7168918