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A
A. Gerosa, Xotta, A., Bevilacqua, A., and Neviani, A., An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Σ Δ Modulator and a Flash Converter, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, pp. 2109 -2124, 2006.
A. Xotta, Vogrig, D., Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., Bruccoleri, M., and Betti, G., An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels, in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, 2002, vol. 5, p. V-69 - V-72 vol.5.
M. PERENZONI, Gerosa, A., and Neviani, A., Analog CMOS Implementation of Gallager’s Interative Decoding algorithm applied to a Block Turbo Code, in ISCAS, 2003, vol. 5, pp. 813–816.
S. Soldà, Vogrig, D., Bevilacqua, A., Gerosa, A., and Neviani, A., Analog decoding of trellis coded modulation for multi-level flash memories, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008., 2008, pp. 744 -747.
A. Gerosa, Novo, A., and Neviani, A., An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process, in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 152 -157.
A. Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS, in Proc. of IEEE 2007 European Solid State Circuits Conference, 2007, pp. 139 -142.
A. G. I. Amatt, Benedetto, S., Montorsi, G., Vogrig, D., Neviani, A., and Gerosa, A., An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code, in Communications, 2005. ICC 2005. 2005 IEEE International Conference on, 2005, vol. 1, pp. 663 - 667 Vol. 1.
A. Graell i Amat, Montorsi, G., Benedetto, S., Vogrig, D., Neviani, A., and Gerosa, A., An analog turbo decoder for the UMTS standard, in Information Theory, 2004. ISIT 2004. Proceedings. International Symposium on, 2004, p. 296.
A. Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., Analysis and Design of an Integrated Notch Filter for the Rejection of Interference in UWB Systems, IEEE Journal of Solid-State Circuits, vol. 44, pp. 331 -343, 2009.
C
P. Scaramuzza, Rubino, C., Tiebout, M., Caruso, M., Ortner, M., Neviani, A., and Bevilacqua, A., Class-AB and class-J 22 dBm SiGe HBT PAs for X-band radar systems, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 187-190.
A. Novo, Gerosa, A., Neviani, A., Mozzi, A., and Zanoni, E., A CMOS 0.8 um programmable charge pump for the output stage of an implantable pacemaker, in Devices, Circuits and Systems, 2000. Proceedings of the 2000 Third IEEE International Caracas Conference on, 2000, pp. 34/1 -34/5.
A. Xotta, Gerosa, A., and Neviani, A., CMOS implementation of all-analogue APP decoders: analysis of performances and limitations, Electronics Letters, vol. 37, pp. 1501 -1503, 2001.
N. Modolo, De Santi, C., Baratella, G., Bettini, A., Borga, M., Posthuma, N., Bakeroot, B., You, S., Decoutere, S., Bevilacqua, A., Neviani, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices, IEEE Transactions on Electron Devices, pp. 1-6, 2022.
A. Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., Neviani, A., and Gerosa, A., CTH08-3: Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code, in Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE, 2006, pp. 1 -6.

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