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A. Bilato, Issakov, V., and Bevilacqua, A., A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.
A. Passamani, Ponton, D., Thaller, E., Knoblinger, G., Neviani, A., and Bevilacqua, A., A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE, in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 232-233.
F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation, IEEE Journal of Solid-State Circuits, vol. 51, pp. 1525-1536, 2016.
F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation, in European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st, 2015, pp. 56-59.
A. Gatti, Spiazzi, G., Gerosa, A., Neviani, A., and Bevilacqua, A., A 130-nm CMOS Dual Input-Polarity DC–DC Converter for Low-Power Applications, IEEE Solid-State Circuits Letters, vol. 2, pp. 211-214, 2019.
F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers, in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 363-366.
S. Veni, Caruso, M., Tiebout, M., and Bevilacqua, A., A 17 GHz All-npn Push-Pull Class-C VCO, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.
M. Bassi, Caruso, M., Bevilacqua, A., and Neviani, A., A 1.75–15 GHz Stepped Frequency Receiver for Breast Cancer Imaging in 65nm CMOS, in Proc. of the IEEE European Solid-State Circuits Conference, 2012, pp. 353–356.
F. Quadrelli, Panazzolo, F., Tiebout, M., Padovan, F., Bassi, M., and Bevilacqua, A., A 18.2-29.3 GHz Colpitts VCOs bank with -119.5 dBc/Hz Phase Noise at 1 MHz Offset for 5G Communications, in 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019.
A. Franceschin, Andreani, P., Padovan, F., Bassi, M., Nonis, R., and Bevilacqua, A., A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion, in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019.
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F. Padovan, Bevilacqua, A., and Neviani, A., A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 287-290.
M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., A 2-16 GHz 65 nm CMOS Stepped-Frequency Radar Transmitter With Harmonic Rejection for High-Resolution Medical Imaging Applications, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 413-422, 2015.
M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., A 2-16GHz 204mW 3mm-Resolution Stepped Frequency Radar for Breast Cancer Diagnostic Imaging in 65nm CMOS, in IEEE ISSCC Digest of Technical Papers, 2013, pp. 204-241.
F. Boscolo, Padovan, F., Quadrelli, F., Tiebout, M., Neviani, A., and Bevilacqua, A., A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 91-94.
A. Bevilacqua and Andreani, P., A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2, in NORCHIP, 2011, 2011, pp. 1 -4.
A. Bevilacqua and Andreani, P., A 2.7–6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, pp. 1–10, 2012.
A. Passamani, Ponton, D., Wolter, A., Knoblinger, G., and Bevilacqua, A., A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm2 Area w/ 2D Digital-Pre-Distortion and Package Combiner, in 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018.

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