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2022
S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.
S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.
S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.
F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.
F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.
F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.
A. Bettini, Cosnier, T., Magnani, A., Syshchyk, O., Borga, M., Decoutere, S., and Neviani, A., Analysis and Design of a Fully-Integrated Pulsed LiDAR Driver in 100V-GaN IC Technology, in 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2022.
F. Quadrelli, Manente, D., Seebacher, D., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications, IEEE Journal of Solid-State Circuits, vol. 57, pp. 1968-1981, 2022.
S. M. Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μ s-Locking-Time, IEEE Journal of Solid-State Circuits, pp. 1-14, 2022.
S. M. Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μ s-Locking-Time, IEEE Journal of Solid-State Circuits, pp. 1-14, 2022.
S. M. Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μ s-Locking-Time, IEEE Journal of Solid-State Circuits, pp. 1-14, 2022.
C. Shi, Song, M., Gao, Z., Bevilacqua, A., Dolmans, G., and Liu, Y. - H., Galvanic-Coupled Trans-Dural Data Transfer for High-Bandwidth Intracortical Neural Sensing, IEEE Transactions on Microwave Theory and Techniques, vol. 70, pp. 4579-4589, 2022.
C. Shi, Song, M., Gao, Z., Bevilacqua, A., Dolmans, G., and Liu, Y. - H., Galvanic-Coupled Trans-Dural Data Transfer for High-Bandwidth Intracortical Neural Sensing, IEEE Transactions on Microwave Theory and Techniques, vol. 70, pp. 4579-4589, 2022.
F. Chiocchetta, De Santi, C., Rampazzo, F., Mukherjee, K., Grünenpütt, J., Sommer, D., Blanck, H., Lambert, B., Gerosa, A., MENEGHESSO, G., Zanoni, E., and Meneghini, M., GaN RF HEMT Reliability: Impact of Device Processing on I-V Curve Stability and Current Collapse, in 2022 IEEE International Reliability Physics Symposium (IRPS), 2022.
2021
S. Veni, Caruso, M., Seebacher, D., Neviani, A., and Bevilacqua, A., A Fully Integrated 28 GHz Class-J Doherty Power Amplifier in 130 nm BiCMOS, in SMACD / PRIME 2021; International Conference on SMACD and 16th Conference on PRIME, 2021.
2020
G. Marin, Kim, J., Seo, J. - M., and Neviani, A., A 13.56 MHz Reconfigurable Step-Up Switched Capacitor Converter for Wireless Power Transfer System in Implantable Medical Devices, in 2020 IEEE Wireless Power Transfer Conference (WPTC), 2020.
D. Manente, Padovan, F., Seebacher, D., Bassi, M., and Bevilacqua, A., A 28-GHz Stacked Power Amplifier with 20.7-dBm Output P1dB in 28-nm Bulk CMOS, IEEE Solid-State Circuits Letters, vol. 3, pp. 170-173, 2020.
S. Marconi, Spiazzi, G., Bevilacqua, A., and Galvano, M., A Novel Integrated Step-Up Hybrid Converter With Wide Conversion Ratio, IEEE Transactions on Power Electronics, vol. 35, pp. 2764-2775, 2020.
G. Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
G. Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
G. Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., A Reconfigurable Switched Capacitor DC–DC Converter With 1.9–6.3-V Input Voltage Range and 85% Peak Efficiency in 28-nm CMOS, IEEE Solid-State Circuits Letters, vol. 3, pp. 106-109, 2020.
G. Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., A Reconfigurable Switched Capacitor DC–DC Converter With 1.9–6.3-V Input Voltage Range and 85% Peak Efficiency in 28-nm CMOS, IEEE Solid-State Circuits Letters, vol. 3, pp. 106-109, 2020.

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