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2023

F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., “A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner”, IEEE Journal of Solid-State Circuits, vol. 58, pp. 634-646, 2023.

F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., “A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner”, IEEE Journal of Solid-State Circuits, vol. 58, pp. 634-646, 2023.

F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. L., and Levantino, S., “A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner”, IEEE Journal of Solid-State Circuits, vol. 58, pp. 634-646, 2023.

A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs”, IEEE Journal of Solid-State Circuits, pp. 1-13, 2023.

A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “Analysis and Design of Coupled PLL-Based CMOS Quadrature VCOs”, IEEE Journal of Solid-State Circuits, pp. 1-13, 2023.

D. Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, pp. 607-617, 2023.

D. Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A Compensation and Calibration Technique for Lumped Hybrid Couplers in Integrated Image-Reject Architectures”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, pp. 607-617, 2023.

N. Zugno, Brandonisio, F., Niederfriniger, T., and Bevilacqua, A., “On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies”, in 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2023.

N. Zugno, Brandonisio, F., Niederfriniger, T., and Bevilacqua, A., “On the Design Challenges of Class-C Oscillators in Ultra-Scaled CMOS Technologies”, in 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2023.

L. Tomasin, Vogrig, D., Neviani, A., and Bevilacqua, A., “A Reactive Passive Mixer for 16-QAM Cartesian IoT Transmitters in 22 nm FD-SOI CMOS”, in 2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2023.

L. Tomasin and Bevilacqua, A., “A Time-Variant Analysis of Passive Resistive Mixers Using Thevenin Theorem”, in 2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2023.

2022

L. Tomasin, Andreani, P., Boi, G., Padovan, F., and Bevilacqua, A., “A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise”, IEEE Journal of Solid-State Circuits, vol. 57, pp. 2802-2811, 2022.

L. Tomasin, Andreani, P., Boi, G., Padovan, F., and Bevilacqua, A., “A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise”, IEEE Journal of Solid-State Circuits, vol. 57, pp. 2802-2811, 2022.

A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS”, in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022.

A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS”, in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022.

S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., “A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching”, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.

S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., “A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching”, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.

S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., “A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching”, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.

F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., “A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler”, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.

F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., “A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler”, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.

F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., “A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler”, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.

A. Bettini, Cosnier, T., Magnani, A., Syshchyk, O., Borga, M., Decoutere, S., and Neviani, A., “Analysis and Design of a Fully-Integrated Pulsed LiDAR Driver in 100V-GaN IC Technology”, in 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2022.

A. Bettini, Cosnier, T., Magnani, A., Syshchyk, O., Borga, M., Decoutere, S., and Neviani, A., “Analysis and Design of a Fully-Integrated Pulsed LiDAR Driver in 100V-GaN IC Technology”, in 2022 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2022.

F. Quadrelli, Manente, D., Seebacher, D., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications”, IEEE Journal of Solid-State Circuits, vol. 57, pp. 1968-1981, 2022.

F. Quadrelli, Manente, D., Seebacher, D., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications”, IEEE Journal of Solid-State Circuits, vol. 57, pp. 1968-1981, 2022.

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