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2022
L. Tomasin
,
Andreani, P.
,
Boi, G.
,
Padovan, F.
, and
Bevilacqua, A.
,
“
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
”
,
IEEE Journal of Solid-State Circuits
, pp. 1-1, 2022.
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S. Mattia Dartizio
,
Buccoleri, F.
,
Tesolin, F.
,
Avallone, L.
,
Santiccioli, A.
,
Iesurum, A.
,
Steffan, G.
,
Cherniak, D.
,
Bertulessi, L.
,
Bevilacqua, A.
,
Samori, C.
,
Lacaita, A. Leonardo
, and
Levantino, S.
,
“
A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
”
, in
2022 IEEE International Solid- State Circuits Conference (ISSCC)
, 2022.
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F. Buccoleri
,
Dartizio, S. M.
,
Tesolin, F.
,
Avallone, L.
,
Santiccioli, A.
,
Lesurum, A.
,
Steffan, G.
,
Bevilacqua, A.
,
Bertulessi, L.
,
Cherniak, D.
,
Samori, C.
,
Lacaita, A. L.
, and
Levantino, S.
,
“
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
”
, in
2022 IEEE Custom Integrated Circuits Conference (CICC)
, 2022.
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2021
P. Andreani
and
Bevilacqua, A.
,
“
Harmonic Oscillators in CMOS—A Tutorial Overview
”
,
IEEE Open Journal of the Solid-State Circuits Society
, vol. 1, pp. 2-17, 2021.
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2020
A. Franceschin
,
Andreani, P.
,
Padovan, F.
,
Bassi, M.
, and
Bevilacqua, A.
,
“
A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects
”
,
IEEE Journal of Solid-State Circuits
, vol. 55, pp. 1842-1853, 2020.
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S. Veni
,
Andreani, P.
,
Caruso, M.
,
Tiebout, M.
, and
Bevilacqua, A.
,
“
Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO
”
,
IEEE Journal of Solid-State Circuits
, vol. 55, pp. 2345-2355, 2020.
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2019
A. Franceschin
,
Andreani, P.
,
Padovan, F.
,
Bassi, M.
,
Nonis, R.
, and
Bevilacqua, A.
,
“
A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion
”
, in
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)
, 2019.
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2018
F. Pepe
,
Bevilacqua, A.
, and
Andreani, P.
,
“
On the Remarkable Performance of the Series-Resonance CMOS Oscillator
”
,
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol. 65, pp. 531-542, 2018.
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2012
A. Bevilacqua
and
Andreani, P.
,
“
A 2.7–6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2
”
,
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
, pp. 1–10, 2012.
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A. Bevilacqua
and
Andreani, P.
,
“
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
”
,
Circuits and Systems I: Regular Papers, IEEE Transactions on
, vol. 59, pp. 938 -945, 2012.
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A. Bevilacqua
and
Andreani, P.
,
“
Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator
”
,
IEEE Transactions on Circuits and Systems II: Express Briefs
, vol. 59, pp. 20 -24, 2012.
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2011
A. Bevilacqua
and
Andreani, P.
,
“
A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2
”
, in
NORCHIP, 2011
, 2011, pp. 1 -4.
DOI
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A. Bevilacqua
and
Andreani, P.
,
“
On the bias noise to phase noise conversion in harmonic oscillators using Groszkowski theory
”
, in
2011 IEEE International Symposium on Circuits and Systems (ISCAS)
, 2011, pp. 217 -220.
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M. Camponeschi
,
Bevilacqua, A.
, and
Andreani, P.
,
“
Time-variant analysis and design of a power efficient ISM-band quadrature receiver
”
,
Analog Integrated Circuits and Signal Processing
, vol. 67, pp. 11-20, 2011.
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2010
M. Camponeschi
,
Bevilacqua, A.
,
Neviani, A.
, and
Andreani, P.
,
“
Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end
”
, in
Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS)
, 2010, pp. 2063 -2066.
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2009
M. Camponeschi
,
Bevilacqua, A.
, and
Andreani, P.
,
“
Analysis and design of a low-power single-stage CMOS wireless receiver
”
, in
Proc. of 2009 NORCHIP
, 2009, pp. 1 -4.
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2005
D. Vogrig
,
Gerosa, A.
,
Neviani, A.
,
Amat, A. G.
,
Montorsi, G.
, and
Benedetto, S.
,
“
A 0.35- mu;m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code
”
,
Solid-State Circuits, IEEE Journal of
, vol. 40, pp. 753 - 762, 2005.
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A. G. I. Amatt
,
Benedetto, S.
,
Montorsi, G.
,
Vogrig, D.
,
Neviani, A.
, and
Gerosa, A.
,
“
An analog turbo decoder for the rate-1/3, 40 bit, UMTS turbo code
”
, in
Communications, 2005. ICC 2005. 2005 IEEE International Conference on
, 2005, vol. 1, pp. 663 - 667 Vol. 1.
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Recent Publications
A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications
Doubly-Tuned Transformer Networks: A Tutorial
More...