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Author Title [ Type

] Year

Book

A. Gerosa, Elettronica Digitale, Esercizi risolti. PADOVA: Edizioni Libreria Progetto, 2006, pp. 1–216.

A. Gerosa, Elettronica Digitale, Esercizi Risolti. PADOVA – ITA: Libreria Progetto, 2004, pp. 1–161.

Book Chapter

A. Bevilacqua, “CMOS UWB Transceivers for Short-Range Microwave Medical Imaging”, in Wireless transceiver circuits, Boca Raton: CRC Press, Taylor & Francis group, 2015, pp. 305–333.

Conference Paper

S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., “A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS”, in Proceedings of ESSCIRC 2009, 2009, pp. 444 -447.

A. Bevilacqua, Vallese, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., “A 0.13 um CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers”, in Digest of Technical Papers of 2007 IEEE International Solid-State Circuits Conference, 2007, pp. 420 -612.

A. Gerosa, Soldan, M., Bevilacqua, A., and Neviani, A., “A 0.18-um CMOS Squarer Circuit for a Non-Coherent UWB Receiver”, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 421 -424.

D. Vogrig, Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., and Benedetto, S., “A 0.35 um CMOS analog turbo decoder for a 40 bit, rate 1/3, UMTS channel code”, in Research in Microelectronics and Electronics, 2005 PhD, 2005, vol. 1, pp. 31 - 34 vol.1.

A. Bevilacqua, Maniero, A., Gerosa, A., and Neviani, A., “A 0.35 um SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection”, in 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06. , 2006, pp. 1015 -1018.

L. Tomasin, Boi, G., Padovan, F., and Bevilacqua, A., “A 10.7–14.1 GHz Reconfigurable Octacore DCO with −126 dBc/Hz Phase Noise at 1 MHz offset in 28 nm CMOS”, in 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2021.

A. Bilato, Issakov, V., and Bevilacqua, A., “A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS”, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.

A. Passamani, Ponton, D., Thaller, E., Knoblinger, G., Neviani, A., and Bevilacqua, A., “A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE”, in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 232-233.

F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., “A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation”, in European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st, 2015, pp. 56-59.

G. Marin, Kim, J., Seo, J. - M., and Neviani, A., “A 13.56 MHz Reconfigurable Step-Up Switched Capacitor Converter for Wireless Power Transfer System in Implantable Medical Devices”, in 2020 IEEE Wireless Power Transfer Conference (WPTC), 2020.

F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., “A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers”, in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 363-366.

S. Veni, Caruso, M., Tiebout, M., and Bevilacqua, A., “A 17 GHz All-npn Push-Pull Class-C VCO”, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.

M. Bassi, Caruso, M., Bevilacqua, A., and Neviani, A., “A 1.75–15 GHz Stepped Frequency Receiver for Breast Cancer Imaging in 65nm CMOS”, in Proc. of the IEEE European Solid-State Circuits Conference, 2012, pp. 353–356.

F. Quadrelli, Panazzolo, F., Tiebout, M., Padovan, F., Bassi, M., and Bevilacqua, A., “A 18.2-29.3 GHz Colpitts VCOs bank with -119.5 dBc/Hz Phase Noise at 1 MHz Offset for 5G Communications”, in 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019.

A. Franceschin, Andreani, P., Padovan, F., Bassi, M., Nonis, R., and Bevilacqua, A., “A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion”, in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019.

F. Padovan, Bevilacqua, A., and Neviani, A., “A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS”, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 287-290.

M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., “A 2-16GHz 204mW 3mm-Resolution Stepped Frequency Radar for Breast Cancer Diagnostic Imaging in 65nm CMOS”, in IEEE ISSCC Digest of Technical Papers, 2013, pp. 204-241.

F. Boscolo, Padovan, F., Quadrelli, F., Tiebout, M., Neviani, A., and Bevilacqua, A., “A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset”, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 91-94.

D. Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A 22–31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS”, in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021.

A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS”, in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022.

A. Bevilacqua and Andreani, P., “A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2”, in NORCHIP, 2011, 2011, pp. 1 -4.

A. Passamani, Ponton, D., Wolter, A., Knoblinger, G., and Bevilacqua, A., “A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm2 Area w/ 2D Digital-Pre-Distortion and Package Combiner”, in 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018.

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