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Conference Paper
A. Bevilacqua, Vallese, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., A 0.13 um CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers, in Digest of Technical Papers of 2007 IEEE International Solid-State Circuits Conference, 2007, pp. 420 -612.
A. Gerosa, Soldan, M., Bevilacqua, A., and Neviani, A., A 0.18-um CMOS Squarer Circuit for a Non-Coherent UWB Receiver, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 421 -424.
A. Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO, in Proceedings of the 32nd European Solid-State Circuits Conference, 2006, pp. 440 -443.
J. Zhao, Bassi, M., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 179-182.
S. Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request, in Proceedings of the ESSCIRC 2010, 2010, pp. 498 -501.
S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.
S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.
S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.
A. Bevilacqua, Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., A 6-9-GHz programmable gain LNA with integrated balun in 90-nm CMOS, in IEEE International Conference on Ultra-Wideband, 2008. ICUWB 2008. , 2008, vol. 1, pp. 25 -28.
F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.
F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.
F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.
S. Soldà, Vogrig, D., Bevilacqua, A., Gerosa, A., and Neviani, A., Analog decoding of trellis coded modulation for multi-level flash memories, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008., 2008, pp. 744 -747.
A. Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS, in Proc. of IEEE 2007 European Solid State Circuits Conference, 2007, pp. 139 -142.
P. Scaramuzza, Rubino, C., Tiebout, M., Caruso, M., Ortner, M., Neviani, A., and Bevilacqua, A., Class-AB and class-J 22 dBm SiGe HBT PAs for X-band radar systems, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 187-190.
A. Gerosa, Soldà, S., Bevilacqua, A., Vogrig, D., and Neviani, A., A digitally programmable ring oscillator in the UWB range, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS),, 2010, pp. 1101 -1104.
S. Veni, Caruso, M., Seebacher, D., Neviani, A., and Bevilacqua, A., A Fully Integrated 28 GHz Class-J Doherty Power Amplifier in 130 nm BiCMOS, in SMACD / PRIME 2021; International Conference on SMACD and 16th Conference on PRIME, 2021.
G. Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., Global Optimization of Reconfigurable Switched Capacitor DC-DC Converters, in 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019.
G. Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., Global Optimization of Reconfigurable Switched Capacitor DC-DC Converters, in 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019.
A. Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., SOLDA, S., Neviani, A., and Gerosa, A., Iterative Analog Decoder for a SCCC, in Analog Decoding Workshop, 2006.
S. Soldà, Caruso, M., Vogrig, D., Bevilacqua, A., Gerosa, A., and Neviani, A., Low-power UWB transmitter using a combined mixer and power amplifier, in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, pp. 333 -336.
A. Gerosa, Bevilacqua, A., and Spiazzi, G., A Multi-Phase Self-Reconfigurable Switched-Capacitor DC-DC Step-Up Converter Integrated in CMOS Technology, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019.
G. Spiazzi, Biadene, D., Marconi, S., and Bevilacqua, A., Non-isolated high step-up DC-DC converter with minimum switch voltage stress, in 2017 IEEE Southern Power Electronics Conference (SPEC), 2017.
A. Bevilacqua and Svelto, F., Non-linear spectral analysis of direct conversion wireless receivers, in IEEE 2002 Radio and Wireless Conference, 2002, pp. 39 - 42.
G. Marin, Cherniak, K., Subotskaya, V., Bodano, E., Sandner, C., and Bevilacqua, A., Optimized Driver Design for Integrated Reconfigurable Switched Capacitor Converters, in 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020.

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