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Conference Paper
S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS, in Proceedings of ESSCIRC 2009, 2009, pp. 444 -447.
A. Bevilacqua, Vallese, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., A 0.13 um CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers, in Digest of Technical Papers of 2007 IEEE International Solid-State Circuits Conference, 2007, pp. 420 -612.
A. Gerosa, Soldan, M., Bevilacqua, A., and Neviani, A., A 0.18-um CMOS Squarer Circuit for a Non-Coherent UWB Receiver, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 421 -424.
D. Vogrig, Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., and Benedetto, S., A 0.35 um CMOS analog turbo decoder for a 40 bit, rate 1/3, UMTS channel code, in Research in Microelectronics and Electronics, 2005 PhD, 2005, vol. 1, pp. 31 - 34 vol.1.
A. Bevilacqua, Maniero, A., Gerosa, A., and Neviani, A., A 0.35 um SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection, in 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06. , 2006, pp. 1015 -1018.
A. Passamani, Ponton, D., Thaller, E., Knoblinger, G., Neviani, A., and Bevilacqua, A., A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE, in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 232-233.
F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation, in European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st, 2015, pp. 56-59.
G. Marin, Kim, J., Seo, J. - M., and Neviani, A., A 13.56 MHz Reconfigurable Step-Up Switched Capacitor Converter for Wireless Power Transfer System in Implantable Medical Devices, in 2020 IEEE Wireless Power Transfer Conference (WPTC), 2020.
F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers, in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 363-366.
M. Bassi, Caruso, M., Bevilacqua, A., and Neviani, A., A 1.75–15 GHz Stepped Frequency Receiver for Breast Cancer Imaging in 65nm CMOS, in Proc. of the IEEE European Solid-State Circuits Conference, 2012, pp. 353–356.
A. Franceschin, Andreani, P., Padovan, F., Bassi, M., Nonis, R., and Bevilacqua, A., A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion, in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019.
F. Padovan, Bevilacqua, A., and Neviani, A., A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 287-290.
M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., A 2-16GHz 204mW 3mm-Resolution Stepped Frequency Radar for Breast Cancer Diagnostic Imaging in 65nm CMOS, in IEEE ISSCC Digest of Technical Papers, 2013, pp. 204-241.
F. Boscolo, Padovan, F., Quadrelli, F., Tiebout, M., Neviani, A., and Bevilacqua, A., A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 91-94.
A. Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO, in Proceedings of the 32nd European Solid-State Circuits Conference, 2006, pp. 440 -443.
A. Bevilacqua, Lorenzon, L., Da Dalt, N., Gerosa, A., and Neviani, A., A 4.1 to 5.1 GHz 430 uA injection-locked frequency divider by 7 in 65 nm CMOS, in Proceedings of the ESSCIRC 2010, 2010, pp. 150 -153.
S. Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request, in Proceedings of the ESSCIRC 2010, 2010, pp. 498 -501.
A. Bevilacqua, Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., A 6-9-GHz programmable gain LNA with integrated balun in 90-nm CMOS, in IEEE International Conference on Ultra-Wideband, 2008. ICUWB 2008. , 2008, vol. 1, pp. 25 -28.
M. Camponeschi, Bevilacqua, A., Neviani, A., and Andreani, P., Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 2063 -2066.
A. Xotta, Vogrig, D., Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., Bruccoleri, M., and Betti, G., An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels, in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, 2002, vol. 5, p. V-69 - V-72 vol.5.
M. PERENZONI, Gerosa, A., and Neviani, A., Analog CMOS Implementation of Gallager’s Interative Decoding algorithm applied to a Block Turbo Code, in ISCAS, 2003, vol. 5, pp. 813–816.
S. Soldà, Vogrig, D., Bevilacqua, A., Gerosa, A., and Neviani, A., Analog decoding of trellis coded modulation for multi-level flash memories, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008., 2008, pp. 744 -747.
A. Gerosa, Novo, A., and Neviani, A., An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process, in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 152 -157.
A. Gerosa, Novo, A., and Neviani, A., An analog front-end for the acquisition of biomedical signals, fully integrated in a 0.8 um CMOS process, in Mixed-Signal Design, 2001. SSMSD. 2001 Southwest Symposium on, 2001, pp. 152 -157.
A. Vallese, Bevilacqua, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., An analog front-end with integrated notch filter for 3-5 GHz UWB receivers in 0.13 um CMOS, in Proc. of IEEE 2007 European Solid State Circuits Conference, 2007, pp. 139 -142.

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