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Integrated Circuits for Analog and RF µ-Systems
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Conference Paper
A. Bilato
,
Issakov, V.
, and
Bevilacqua, A.
,
“
A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS
”
, in
2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS)
, 2019.
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S. Mattia Dartizio
,
Buccoleri, F.
,
Tesolin, F.
,
Avallone, L.
,
Santiccioli, A.
,
Iesurum, A.
,
Steffan, G.
,
Cherniak, D.
,
Bertulessi, L.
,
Bevilacqua, A.
,
Samori, C.
,
Lacaita, A. Leonardo
, and
Levantino, S.
,
“
A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
”
, in
2022 IEEE International Solid- State Circuits Conference (ISSCC)
, 2022.
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A. Bilato
,
Issakov, V.
, and
Bevilacqua, A.
,
“
Considerations on 120GHz LO Signal Generation and Distribution for Highly-Integrated Multi-Channel Radar Transceivers
”
, in
2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS)
, 2019.
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Journal Article
A. Bilato
,
Issakov, V.
,
Mazzanti, A.
, and
Bevilacqua, A.
,
“
A Multichannel D-Band Radar Receiver With Optimized LO Distribution
”
,
IEEE Solid-State Circuits Letters
, vol. 4, pp. 141-144, 2021.
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Recent Publications
A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications
Compact Modeling of Nonideal Trapping/Detrapping Processes in GaN Power Devices
More...