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S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., A 0.059-mm2 10.8-mW local oscillator for GSM systems in 65-nm CMOS, in Proceedings of ESSCIRC 2009, 2009, pp. 444 -447.
S. Dal Toso, Bevilacqua, A., Tiebout, M., Da Dalt, N., Gerosa, A., and Neviani, A., A 0.06 mm2 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS, IEEE Journal of Solid-State Circuits, vol. 45, pp. 1295 -1304, 2010.
A. Bevilacqua, Vallese, A., Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., A 0.13 um CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers, in Digest of Technical Papers of 2007 IEEE International Solid-State Circuits Conference, 2007, pp. 420 -612.
A. Gerosa, Soldan, M., Bevilacqua, A., and Neviani, A., A 0.18-um CMOS Squarer Circuit for a Non-Coherent UWB Receiver, in IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 2007, pp. 421 -424.
D. Vogrig, Gerosa, A., Neviani, A., Amat, A. G., Montorsi, G., and Benedetto, S., A 0.35- mu;m CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code, Solid-State Circuits, IEEE Journal of, vol. 40, pp. 753 - 762, 2005.
D. Vogrig, Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., and Benedetto, S., A 0.35 um CMOS analog turbo decoder for a 40 bit, rate 1/3, UMTS channel code, in Research in Microelectronics and Electronics, 2005 PhD, 2005, vol. 1, pp. 31 - 34 vol.1.
A. Bevilacqua, Maniero, A., Gerosa, A., and Neviani, A., A 0.35 um SiGe Low-Noise Amplifier for UWB, Receivers with Integrated Interferer Rejection, in 13th IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06. , 2006, pp. 1015 -1018.
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L. Tomasin, Boi, G., Padovan, F., and Bevilacqua, A., A 10.7–14.1 GHz Reconfigurable Octacore DCO with −126 dBc/Hz Phase Noise at 1 MHz offset in 28 nm CMOS, in 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2021.
A. Bilato, Issakov, V., and Bevilacqua, A., A 114-126 GHz Frequency Quintupler with >36 dBc Harmonic Rejection in 0.13 μm SiGe BiCMOS, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.
A. Passamani, Ponton, D., Thaller, E., Knoblinger, G., Neviani, A., and Bevilacqua, A., A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE, in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 232-233.
F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., A 12 GHz 22 dB-Gain-Control SiGe Bipolar VGA With 2° Phase-Shift Variation, IEEE Journal of Solid-State Circuits, vol. 51, pp. 1525-1536, 2016.
F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation, in European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st, 2015, pp. 56-59.
L. Tomasin, Andreani, P., Boi, G., Padovan, F., and Bevilacqua, A., A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise, IEEE Journal of Solid-State Circuits, pp. 1-1, 2022.
A. Gatti, Spiazzi, G., Gerosa, A., Neviani, A., and Bevilacqua, A., A 130-nm CMOS Dual Input-Polarity DC–DC Converter for Low-Power Applications, IEEE Solid-State Circuits Letters, vol. 2, pp. 211-214, 2019.
F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers, in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 363-366.
S. Veni, Caruso, M., Tiebout, M., and Bevilacqua, A., A 17 GHz All-npn Push-Pull Class-C VCO, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.
M. Bassi, Caruso, M., Bevilacqua, A., and Neviani, A., A 1.75–15 GHz Stepped Frequency Receiver for Breast Cancer Imaging in 65nm CMOS, in Proc. of the IEEE European Solid-State Circuits Conference, 2012, pp. 353–356.
F. Quadrelli, Panazzolo, F., Tiebout, M., Padovan, F., Bassi, M., and Bevilacqua, A., A 18.2-29.3 GHz Colpitts VCOs bank with -119.5 dBc/Hz Phase Noise at 1 MHz Offset for 5G Communications, in 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019.
A. Gerosa and Neviani, A., A 1.8uW Sigma-Delta Modulator for 8-bit Digitization of Cardiac Signals in Implantable Pacemakers Operating Down to 1.8V, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. II, EXPRESS BRIEFS, vol. 52, pp. 71–76, 2005.
A. Franceschin, Andreani, P., Padovan, F., Bassi, M., Nonis, R., and Bevilacqua, A., A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion, in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019.
A. Franceschin, Andreani, P., Padovan, F., Bassi, M., and Bevilacqua, A., A 19.5-GHz 28-nm Class-C CMOS VCO, With a Reasonably Rigorous Result on 1/f Noise Upconversion Caused by Short-Channel Effects, IEEE Journal of Solid-State Circuits, vol. 55, pp. 1842-1853, 2020.

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