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A. Graell i Amat, Benedetto, S., Montorsi, G., Vogrig, D., Neviani, A., and Gerosa, A., Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code, Communications, IEEE Transactions on, vol. 54, pp. 1973 -1982, 2006.
A. Graell i Amat, Montorsi, G., Benedetto, S., Vogrig, D., Neviani, A., and Gerosa, A., An analog turbo decoder for the UMTS standard, in Information Theory, 2004. ISIT 2004. Proceedings. International Symposium on, 2004, p. 296.
A. Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., SOLDA, S., Neviani, A., and Gerosa, A., Iterative Analog Decoder for a SCCC, in Analog Decoding Workshop, 2006.
A. Graell i Amat, Vogrig, D., Benedetto, S., Montorsi, G., Neviani, A., and Gerosa, A., CTH08-3: Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code, in Global Telecommunications Conference, 2006. GLOBECOM '06. IEEE, 2006, pp. 1 -6.
A. Gerosa, A ready-to-use design procedure for operational transconductance amplifiers that minimizes power consumption, in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, 2001, vol. 2, pp. 949 -952 vol.2.
A. Gerosa, Xotta, A., Neviani, A., and Mian, G. A., Frequency Offset Compensation in Fractionally Spaced Equalization, IEE PROCEEDINGS. CIRCUITS, DEVICES AND SYSTEMS, vol. 150, pp. 134–140, 2003.
A. Gerosa, Bevilacqua, A., and Neviani, A., A local oscillator for WCDMA band VII based on frequency multiplication, Analog Integrated Circuits and Signal Processing, vol. 72, no. 1, 2012.
A. Gerosa, Costa, M. D., Bevilacqua, A., Vogrig, D., and Neviani, A., An energy-detector for non-coherent impulse-radio UWB receivers, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008, 2008, pp. 2705 -2708.
A. Gerosa, Novo, A., Mengalli, A., and Neviani, A., A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker, in Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, 2001, vol. 1, pp. 296 -299 vol. 1.
A. Gerosa, Design of Power-Optimized OTAs for SC Applications. 2001.
A. Gerosa, Neviani, A., and Maniero, A., A Fully-Integrated Two-Channel A/D Interface for the Acquisition of Cardiac Signals in Implantable Pacemakers, IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 39, pp. 1083–1093, 2004.
A. Gerosa and Mian, G. A., A low complexity EPR-IV equalizer for hard disk read channels, in Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on, 1999, vol. 2, pp. 1069 -1072 vol.2.
A. Gerosa, Maniero, A., and Neviani, A., A Fully-Integrated Two-Channel A/D Interface for the Acquisition of Cardiac Signals in Implantable Pacemakers, in ESSCIRC, 2003, vol. 1, pp. 157–160.
A. Gerosa, Soldà, S., Bevilacqua, A., Vogrig, D., and Neviani, A., An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, pp. 1030 -1040, 2009.
A. Gerosa, Neviani, A., Xotta, A., and Mian, G. A., A novel architecture to reduce complexity in hard disk read channel based on fractionally spaced equalization, in Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on, 2001, vol. 2, pp. 1099 -1102 vol.2.
A. Gerosa, Neviani, A., and Zanoni, E., A SC Video Filter with Analog-RAM-based Delay Efficient Realization, in ECCTD, 1999, vol. 2, pp. 1247–1250.
A. Gerosa, Elettronica Digitale, Esercizi Risolti. PADOVA – ITA: Libreria Progetto, 2004, pp. 1–161.
A. Gerosa, Xotta, A., Bevilacqua, A., and Neviani, A., An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling Σ Δ Modulator and a Flash Converter, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, pp. 2109 -2124, 2006.
A. Gerosa, Neviani, A., and Cortelazzo, G. M., A partial accumulation analog-RAM-based architecture for delay efficient realization of 2D SC FIR filters, in Mixed-Signal Design, 1999. SSMSD '99. 1999 Southwest Symposium on, 1999, pp. 195 -198.
A. Gerosa and Neviani, A., A Very Low-Power 8-bit Sigma-Delta Converter in a 0.8um CMOS Technology for the Sensing Chain of a Cardiac Pacemaker, Operating down to 1.8V, in ISCAS, 2003, vol. 5, pp. 49–52.
A. Gerosa, Elettronica Digitale, Esercizi risolti. PADOVA: Edizioni Libreria Progetto, 2006, pp. 1–216.
A. Gerosa, Soldà, S., Bevilacqua, A., Vogrig, D., and Neviani, A., A digitally programmable ring oscillator in the UWB range, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS),, 2010, pp. 1101 -1104.
A. Gerosa, Novo, A., and Neviani, A., Low-power sensing and digitization of cardiac signals based on sigma-delta conversion, in Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on, 2000, pp. 216 - 218.
A. Gerosa and Mian, G. A., An Equalizer for Hard Disk Drive Channels, with Low Sensitivity to Sampling Phase Variation, in EUSIPCO-98, 1998, vol. 1, pp. 483–486.
A. Gerosa and Neviani, A., A LOW-POWER DECIMATION FILTER FOR A SIGMA-DELTA CONVERTER BASED ON A POWER-OPTMIZED SINC FILTER, in ISCAS, 2004, vol. 2, pp. 245–248.

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