You are here

Biblio

Export 185 results:

Author Title [ Type

] Year

Conference Paper

A. Xotta, Vogrig, D., Gerosa, A., Neviani, A., Graell i Amat, A., Montorsi, G., Bruccoleri, M., and Betti, G., “An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels”, in Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on, 2002, vol. 5, p. V-69 - V-72 vol.5.

M. Camponeschi, Bevilacqua, A., Neviani, A., and Andreani, P., “Accurate time-variant analysis of a current-reuse 2.2 GHz 1.3 mW CMOS front-end”, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, pp. 2063 -2066.

F. Buccoleri, Dartizio, S. M., Tesolin, F., Avallone, L., Santiccioli, A., Lesurum, A., Steffan, G., Bevilacqua, A., Bertulessi, L., Cherniak, D., Samori, C., Lacaita, A. L., and Levantino, S., “A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler”, in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.

A. Bevilacqua, Sandner, C., Tiebout, M., Gerosa, A., and Neviani, A., “A 6-9-GHz programmable gain LNA with integrated balun in 90-nm CMOS”, in IEEE International Conference on Ultra-Wideband, 2008. ICUWB 2008. , 2008, vol. 1, pp. 25 -28.

S. Mattia Dartizio, Buccoleri, F., Tesolin, F., Avallone, L., Santiccioli, A., Iesurum, A., Steffan, G., Cherniak, D., Bertulessi, L., Bevilacqua, A., Samori, C., Lacaita, A. Leonardo, and Levantino, S., “A 68.6fs_rms-Total-integrated-Jitter and 1.5μs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching”, in 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022.

S. Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., “A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request”, in Proceedings of the ESSCIRC 2010, 2010, pp. 498 -501.

L. Grimaldi, Iesurum, A., Boi, G., Versolatto, F., Steffan, G., Padovan, F., Koltsov, H., Bevilacqua, A., and Cherniak, D., “A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs”, in 2024 IEEE European Solid-State Electronics Research Conference (ESSERC), 2024.

A. Bevilacqua, Lorenzon, L., Da Dalt, N., Gerosa, A., and Neviani, A., “A 4.1 to 5.1 GHz 430 uA injection-locked frequency divider by 7 in 65 nm CMOS”, in Proceedings of the ESSCIRC 2010, 2010, pp. 150 -153.

J. Zhao, Bassi, M., Bevilacqua, A., Ghilioni, A., Mazzanti, A., and Svelto, F., “A 40-67GHz power amplifier with 13dBm PSAT and 16% PAE in 28 nm CMOS LP”, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 179-182.

A. Bevilacqua, Pavan, F. P., Sandner, C., Gerosa, A., and Neviani, A., “A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO”, in Proceedings of the 32nd European Solid-State Circuits Conference, 2006, pp. 440 -443.

A. Passamani, Ponton, D., Wolter, A., Knoblinger, G., and Bevilacqua, A., “A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm2 Area w/ 2D Digital-Pre-Distortion and Package Combiner”, in 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018.

A. Bevilacqua and Andreani, P., “A 2.7-6.1GHz CMOS local oscillator based on frequency multiplication by 3/2”, in NORCHIP, 2011, 2011, pp. 1 -4.

A. Iesurum, Manente, D., Padovan, F., Bassi, M., and Bevilacqua, A., “A 24 GHz Quadrature VCO Based on Coupled PLL with -134 dBc/Hz Phase Noise at 10 MHz Offset in 28 nm CMOS”, in ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), 2022.

D. Manente, Quadrelli, F., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A 22–31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS”, in ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021.

F. Boscolo, Padovan, F., Quadrelli, F., Tiebout, M., Neviani, A., and Bevilacqua, A., “A 21GHz 20.5%-tuning range Colpitts VCO with -119 dBc/Hz phase noise at 1MHz offset”, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 91-94.

M. Caruso, Bassi, M., Bevilacqua, A., and Neviani, A., “A 2-16GHz 204mW 3mm-Resolution Stepped Frequency Radar for Breast Cancer Diagnostic Imaging in 65nm CMOS”, in IEEE ISSCC Digest of Technical Papers, 2013, pp. 204-241.

F. Padovan, Bevilacqua, A., and Neviani, A., “A 20Mb/s, 2.76 pJ/b UWB impulse radio TX with 11.7% efficiency in 130 nm CMOS”, in European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, 2014, pp. 287-290.

A. Franceschin, Andreani, P., Padovan, F., Bassi, M., Nonis, R., and Bevilacqua, A., “A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion”, in ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019.

F. Quadrelli, Panazzolo, F., Tiebout, M., Padovan, F., Bassi, M., and Bevilacqua, A., “A 18.2-29.3 GHz Colpitts VCOs bank with -119.5 dBc/Hz Phase Noise at 1 MHz Offset for 5G Communications”, in 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019.

M. Bassi, Caruso, M., Bevilacqua, A., and Neviani, A., “A 1.75–15 GHz Stepped Frequency Receiver for Breast Cancer Imaging in 65nm CMOS”, in Proc. of the IEEE European Solid-State Circuits Conference, 2012, pp. 353–356.

S. Veni, Caruso, M., Tiebout, M., and Bevilacqua, A., “A 17 GHz All-npn Push-Pull Class-C VCO”, in 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019.

F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., “A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers”, in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 363-366.

G. Marin, Kim, J., Seo, J. - M., and Neviani, A., “A 13.56 MHz Reconfigurable Step-Up Switched Capacitor Converter for Wireless Power Transfer System in Implantable Medical Devices”, in 2020 IEEE Wireless Power Transfer Conference (WPTC), 2020.

F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., “A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation”, in European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015 - 41st, 2015, pp. 56-59.

A. Passamani, Ponton, D., Thaller, E., Knoblinger, G., Neviani, A., and Bevilacqua, A., “A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE”, in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 232-233.

Pages