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P

F. Padovan, Tiebout, M., Mertens, K. L. R., Bevilacqua, A., and Neviani, A., “Design of Low-Noise K -Band SiGe Bipolar VCOs: Theory and Implementation”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 62, pp. 607-615, 2015.

F. Padovan, Tiebout, M., Dielacher, F., Bevilacqua, A., and Neviani, A., “SiGe BiCMOS VCO with 27% tuning range for 5G communications”, in 2015 Asia-Pacific Microwave Conference (APMC), 2015, vol. 1, pp. 1-3.

F. Padovan, Tiebout, M., Neviani, A., and Bevilacqua, A., “A 15.5-39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers”, in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, pp. 363-366.

F. Padovan, Tiebout, M., Mertens, K., Bevilacqua, A., and Neviani, A., “A K-band SiGe bipolar VCO with transformer-coupled varactor for backhaul links”, in 2013 IEEE 13th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF),, 2013, pp. 108-110.

A. Passamani, Ponton, D., Wolter, A., Knoblinger, G., and Bevilacqua, A., “A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm2 Area w/ 2D Digital-Pre-Distortion and Package Combiner”, in 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018.

A. Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., “A linear model of efficiency for Switched-Capacitor RF Power-Amplifiers”, in 2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), 2014, pp. 1-4.

A. Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., “Analysis and design of power and efficiency in third-order matching networks for switched-capacitor power-amplifiers”, Analog Integrated Circuits and Signal Processing, vol. 89, no. 2, pp. 307-315, 2016.

A. Passamani, Ponton, D., Thaller, E., Knoblinger, G., Neviani, A., and Bevilacqua, A., “A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE”, in 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 232-233.

A. Passamani, Ponton, D., Knoblinger, G., and Bevilacqua, A., “Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs”, in Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC), 2015, 2015, pp. 1-4.

D. Pecile, Gambarrucci, A., Kokorovic, S., and Bevilacqua, A., “A Study of the Efficiency of Output-Matched Radiofrequency Power Amplifiers”, Analog Integrated Circuits and Signal Processing, vol. 125, no. 3, p. 42, 2025.

D. Pecile, Kokorovic, S., Gambarucci, A., and Bevilacqua, A., “On the Efficiency of Output-Matched Radiofrequency Power Amplifiers”, in 2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), 2024.

D. Pecile, Kokorovic, S., Gambarucci, A., and Bevilacqua, A., “A 5.1–10.5 GHz SiGe BiCMOS Power Amplifier for 6GNR with 29 dBm PSAT and 40.1% PAE”, in 2025 IEEE 24th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2025.

D. Pecile, Pollin, A., Dal Maistro, D., Gambarucci, A., De Astis, G., and Bevilacqua, A., “A 5-7 GHz BiCMOS Front-End Module for WiFi 6e with 2.2 dB NF and 16 dBm PAVG at −40 dB EVM”, in 2025 20th European Microwave Integrated Circuits Conference (EuMIC), 2025.

D. Pecile, Gambarucci, A., Kokorovic, S., and Bevilacqua, A., “Analysis and Design of a SiGe BiCMOS PA for 6G FR3 Band With 29-dBm P SAT and 40.1% PAE”, IEEE Transactions on Microwave Theory and Techniques, pp. 1-12, 2025.

F. Pepe, Bevilacqua, A., and Andreani, P., “On the Remarkable Performance of the Series-Resonance CMOS Oscillator”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, pp. 531-542, 2018.

M. PERENZONI, Gerosa, A., and Neviani, A., “Analog CMOS Implementation of Gallager’s Interative Decoding algorithm applied to a Block Turbo Code”, in ISCAS, 2003, vol. 5, pp. 813–816.

Q

F. Quadrelli, Manente, D., Seebacher, D., Padovan, F., Bassi, M., Mazzanti, A., and Bevilacqua, A., “A Broadband 22-31-GHz Bidirectional Image-Reject Up/Down Converter Module in 28-nm CMOS for 5G Communications”, IEEE Journal of Solid-State Circuits, vol. 57, pp. 1968-1981, 2022.

F. Quadrelli, Panazzolo, F., Tiebout, M., Padovan, F., Bassi, M., and Bevilacqua, A., “A 18.2-29.3 GHz Colpitts VCOs bank with -119.5 dBc/Hz Phase Noise at 1 MHz Offset for 5G Communications”, in 2019 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2019.

R

M. Ruzzarin, Meneghini, M., de Santi, C., Neviani, A., Yu, F., Strempel, K., Fatahilah, M. Fahlesa, Witzigmann, B., Wasisto, H. Suryo, Waag, A., Meneghesso, G., and Zanoni, E., “Demonstration of UV-Induced Threshold Voltage Instabilities in Vertical GaN Nanowire Array-Based Transistors”, IEEE Transactions on Electron Devices, vol. 66, pp. 2119-2124, 2019.

S

P. Scaramuzza, Rubino, C., Tiebout, M., Caruso, M., Ortner, M., Neviani, A., and Bevilacqua, A., “Class-AB and class-J 22 dBm SiGe HBT PAs for X-band radar systems”, in ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, 2017, pp. 187-190.

P. Scaramuzza, Rubino, C., Caruso, M., Tiebout, M., Bevilacqua, A., and Neviani, A., “Class-J SiGe X-Band Power Amplifier Using a Ladder Filter-Based AM-PM Distortion Reduction Technique”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 11, pp. 3780 - 3789, 2018.

C. Shi, Song, M., Gao, Z., Bevilacqua, A., Dolmans, G., and Liu, Y. - H., “Galvanic-Coupled Trans-Dural Data Transfer for High-Bandwidth Intracortical Neural Sensing”, IEEE Transactions on Microwave Theory and Techniques, vol. 70, pp. 4579-4589, 2022.

S. Soldà, Caruso, M., Vogrig, D., Bevilacqua, A., Gerosa, A., and Neviani, A., “Low-power UWB transmitter using a combined mixer and power amplifier”, in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, pp. 333 -336.

S. Soldà, Caruso, M., Bevilacqua, A., Gerosa, A., Vogrig, D., and Neviani, A., “A 5Mb/s UWB-IR CMOS transceiver with a 186 pJ/b and 150 pJ/b TX/RX energy request”, in Proceedings of the ESSCIRC 2010, 2010, pp. 498 -501.

S. Soldà, Vogrig, D., Bevilacqua, A., Gerosa, A., and Neviani, A., “Analog decoding of trellis coded modulation for multi-level flash memories”, in IEEE International Symposium on Circuits and Systems, 2008. ISCAS 2008., 2008, pp. 744 -747.

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